quartus fft IP核问题

wwxn 2018-09-17 06:37:11

新手刚学FPGA，想做一个正弦信号的频谱分析，用到了FFT，但是输出数据有误，请问是哪里发生了错误？时序如下

部分代码：顶层模块：

module fpga_project

(

	input clk,

	input rst,

	output [7:0] data_f,

	output [7:0] data_out,

	output [7:0] data_ima,

	output [5:0] source_exp,

	output sop,

	output eop,

	output[1:0] error,

	output source_valid,

	output source_sop,

	output source_eop,

	output sink_ready,

	output sink_valid

);

wire[7:0] data;

assign data_f=data+8'h80;//将无符号数转换成有符号数



fft f2 (

	.clk(clk),

	.reset_n(rst),

	.inverse(1'b0),

	.sink_valid(sink_valid),

	.sink_sop(sop),

	.sink_eop(eop),

	.sink_real(data_f),

	.sink_imag(data_f),

	.sink_error(2'b00),

	.source_ready(1'b1),

	.sink_ready(sink_ready),

	.source_error(error),

	.source_sop(source_sop),

	.source_eop(source_eop),

	.source_valid(source_valid),

	.source_exp(source_exp),

	.source_real(data_out),

	.source_imag(data_ima));

sine s1 (.clk(clk),.rst(rst),.out(data),.clk_1(),.sop(sop),.eop(eop),.sink_valid(sink_valid));

endmodule

sin函数产生及FFT控制模块：

module sine(clk,rst,out,clk_1,sop,eop,sink_valid);

input clk;

input rst;

output reg sink_valid;

output [7:0] out;

output clk_1;

output reg sop;

output reg eop;

reg [10:0] num;

reg clk_1;

reg [7:0] addr;

reg [7:0] out;





always@(posedge clk or negedge rst)

if(!rst)

begin

			addr<=8'd255;

			eop<=1'b0;

			sop<=1'b0;

			sink_valid<=1'b0;

			out<=7'b0;

end

else 

begin

	addr=addr+1;

	case(addr)

8'd0:begin

	sink_valid<=1'b1;

	out<=8'h80;

	sop<=1'b1;

	eop<=1'b0;

	end

8'd1:

begin 

out<=8'h83;

sop<=1'b0;

end		

8'd2:out=8'h86;

8'd3:out=8'h89;

8'd4:out=8'h8d;

8'd5:out=8'h90;

8'd6:out=8'h93;

8'd7:out=8'h96;

8'd8:out=8'h99;

8'd9:out=8'h9c;

8'd10:out=8'h9f;

8'd11:out=8'ha2;

8'd12:out=8'ha5;

8'd13:out=8'ha8;

8'd14:out=8'hab;

8'd15:out=8'hae;

8'd16:out=8'hb1;

8'd17:out=8'hb4;

8'd18:out=8'hb7;

8'd19:out=8'hba;

8'd20:out=8'hbc;

8'd21:out=8'hbf;

8'd22:out=8'hc2;

8'd23:out=8'hc5;

8'd24:out=8'hc7;

8'd25:out=8'hca;

8'd26:out=8'hcc;

8'd27:out=8'hcf;

8'd28:out=8'hd1;

8'd29:out=8'hd4;

8'd30:out=8'hd6;

8'd31:out=8'hd8;

8'd32:out=8'hda;

8'd33:out=8'hdd;

8'd34:out=8'hdf;

8'd35:out=8'he1;

8'd36:out=8'he3;

8'd37:out=8'he5;

8'd38:out=8'he7;

8'd39:out=8'he9;

8'd40:out=8'hea;

8'd41:out=8'hec;

8'd42:out=8'hee;

8'd43:out=8'hef;

8'd44:out=8'hf1;

8'd45:out=8'hf2;

8'd46:out=8'hf4;

8'd47:out=8'hf5;

8'd48:out=8'hf6;

8'd49:out=8'hf7;

8'd50:out=8'hf8;

8'd51:out=8'hf9;

8'd52:out=8'hfa;

8'd53:out=8'hfb;

8'd54:out=8'hfc;

8'd55:out=8'hfd;

8'd56:out=8'hfd;

8'd57:out=8'hfe;

8'd58:out=8'hff;

8'd59:out=8'hff;

8'd60:out=8'hff;

8'd61:out=8'hff;

8'd62:out=8'hff;

8'd63:out=8'hff;

8'd64:out=8'hff;

8'd65:out=8'hff;

8'd66:out=8'hff;

8'd67:out=8'hff;

8'd68:out=8'hff;

8'd69:out=8'hff;

8'd70:out=8'hfe;

8'd71:out=8'hfd;

8'd72:out=8'hfd;

8'd73:out=8'hfc;

8'd74:out=8'hfb;

8'd75:out=8'hfa;

8'd76:out=8'hf9;

8'd77:out=8'hf8;

8'd78:out=8'hf7;

8'd79:out=8'hf6;

8'd80:out=8'hf5;

8'd81:out=8'hf4;

8'd82:out=8'hf2;

8'd83:out=8'hf1;

8'd84:out=8'hef;

8'd85:out=8'hee;

8'd86:out=8'hec;

8'd87:out=8'hea;

8'd88:out=8'he9;

8'd89:out=8'he7;

8'd90:out=8'he5;

8'd91:out=8'he3;

8'd92:out=8'he1;

8'd93:out=8'hde;

8'd94:out=8'hdd;

8'd95:out=8'hda;

8'd96:out=8'hd8;

8'd97:out=8'hd6;

8'd98:out=8'hd4;

8'd99:out=8'hd1;

8'd100:out=8'hcf;

8'd101:out=8'hcc;

8'd102:out=8'hca;

8'd103:out=8'hc7;

8'd104:out=8'hc5;

8'd105:out=8'hc2;

8'd106:out=8'hbf;

8'd107:out=8'hbc;

8'd108:out=8'hba;

8'd109:out=8'hb7;

8'd110:out=8'hb4;

8'd111:out=8'hb1;

8'd112:out=8'hae;

8'd113:out=8'hab;

8'd114:out=8'ha8;

8'd115:out=8'ha5;

8'd116:out=8'ha2;

8'd117:out=8'h9f;

8'd118:out=8'h9c;

8'd119:out=8'h99;

8'd120:out=8'h96;

8'd121:out=8'h93;

8'd122:out=8'h90;

8'd123:out=8'h8d;

8'd124:out=8'h89;

8'd125:out=8'h86;

8'd126:out=8'h83;

8'd127:out=8'h80;

8'd128:out=8'h80;

8'd129:out=8'h7c;

8'd130:out=8'h79;

8'd131:out=8'h76;

8'd132:out=8'h72;

8'd133:out=8'h6f;

8'd134:out=8'h6c;

8'd135:out=8'h69;

8'd136:out=8'h66;

8'd137:out=8'h63;

8'd138:out=8'h60;

8'd139:out=8'h5d;

8'd140:out=8'h5a;

8'd141:out=8'h57;

8'd142:out=8'h55;

8'd143:out=8'h51;

8'd144:out=8'h4e;

8'd145:out=8'h4c;

8'd146:out=8'h48;

8'd147:out=8'h45;

8'd148:out=8'h43;

8'd149:out=8'h40;

8'd150:out=8'h3d;

8'd151:out=8'h3a;

8'd152:out=8'h38;

8'd153:out=8'h35;

8'd154:out=8'h33;

8'd155:out=8'h30;

8'd156:out=8'h2e;

8'd157:out=8'h2b;

8'd158:out=8'h29;

8'd159:out=8'h27;

8'd160:out=8'h25;

8'd161:out=8'h22;

8'd162:out=8'h20;

8'd163:out=8'h1e;

8'd164:out=8'h1c;

8'd165:out=8'h1a;

8'd166:out=8'h18;

8'd167:out=8'h16 ;

8'd168:out=8'h15;

8'd169:out=8'h13;

8'd170:out=8'h11;

8'd171:out=8'h10;

8'd172:out=8'h0e;

8'd173:out=8'h0d;

8'd174:out=8'h0b;

8'd175:out=8'h0a;

8'd176:out=8'h09;

8'd177:out=8'h08;

8'd178:out=8'h07;

8'd179:out=8'h06;

8'd180:out=8'h05;

8'd181:out=8'h04;

8'd182:out=8'h03;

8'd183:out=8'h02;

8'd184:out=8'h02;

8'd185:out=8'h01;

8'd186:out=8'h00;

8'd187:out=8'h00;

8'd188:out=8'h00;

8'd189:out=8'h00;

8'd190:out=8'h00;

8'd191:out=8'h00;

8'd192:out=8'h00;

8'd193:out=8'h00;

8'd194:out=8'h00;

8'd195:out=8'h00;

8'd196:out=8'h00;

8'd197:out=8'h00;

8'd198:out=8'h01;

8'd199:out=8'h02 ;

8'd200:out=8'h02;

8'd201:out=8'h03;

8'd202:out=8'h04;

8'd203:out=8'h05;

8'd204:out=8'h06;

8'd205:out=8'h07;

8'd206:out=8'h08;

8'd207:out=8'h09;

8'd208:out=8'h0a;

8'd209:out=8'h0b;

8'd210:out=8'h0d;

8'd211:out=8'h0e;

8'd212:out=8'h10;

8'd213:out=8'h11;

8'd214:out=8'h13;

8'd215:out=8'h15 ;

8'd216:out=8'h16;

8'd217:out=8'h18;

8'd218:out=8'h1a;

8'd219:out=8'h1c;

8'd220:out=8'h1e;

8'd221:out=8'h20;

8'd222:out=8'h22;

8'd223:out=8'h25;

8'd224:out=8'h27;

8'd225:out=8'h29;

8'd226:out=8'h2b;

8'd227:out=8'h2e;

8'd228:out=8'h30;

8'd229:out=8'h33;

8'd230:out=8'h35;

8'd231:out=8'h38;

8'd232:out=8'h3a;

8'd233:out=8'h3d;

8'd234:out=8'h40;

8'd235:out=8'h43;

8'd236:out=8'h45;

8'd237:out=8'h48;

8'd238:out=8'h4c;

8'd239:out=8'h4e;

8'd240:out=8'h51;

8'd241:out=8'h55;

8'd242:out=8'h57;

8'd243:out=8'h5a;

8'd244:out=8'h5d;

8'd245:out=8'h60;

8'd246:out=8'h63;

8'd247:out=8'h66 ;

8'd248:out=8'h69;

8'd249:out=8'h6c;

8'd250:out=8'h6f;

8'd251:out=8'h72;

8'd252:out=8'h76;

8'd253:out=8'h79;

8'd254:out=8'h7c;

8'd255:begin

      out<=8'h80;

     eop<=1'b1;

end



endcase

end

endmodule

testbench:

`timescale 1ns/1ns





module fpga_project_tb();

	reg clk;

	reg rst;

	wire [7:0] data_out;

	wire [7:0] data_ima;

   wire [7:0] data_f;

	wire [5:0] source_exp;

   wire sop;

	wire eop;

	wire[1:0] error;

	wire source_valid;

	wire source_sop;

	wire source_eop;

	wire sink_ready;

	wire sink_valid;

fpga_project f1 

(

	clk,

	rst,

	data_f,

	data_out,

	data_ima,

	source_exp,

	sop,

	eop,

	error,

	source_valid,

	source_sop,

	source_eop,

	sink_ready,

	sink_valid

);

initial

begin

	clk<=1'b0;

	rst<=1'b1;

	#10 rst<=1'b0;

	#10 rst<=1'b1;

end



always #10 clk<=~clk;



endmodule