Verilog HDL 32x32 寄存器堆

[那是一段痛苦的记忆]

module mem1x32(outdata,indata,writeEn,clk,rst);

output reg [31:0] outdata;//读端口
input [31:0] indata;
input writeEn;
input clk;
input rst;

always@(posedge clk)
begin
if(rst)
outdata<=32'd0;
else
begin
if(writeEn)
outdata<=indata;
end
end
endmodule

module mux32_1(outd,in0,in1,in2,in3,in4,in5,in6,in7,in8,in9,
in10,in11,in12,in13,in14,in15,in16,in17,in18,in19,
in20,in21,in22,in23,in24,in25,in26,in27,in28,in29,
in30,in31,addr);

output reg [31:0] outd;
input [31:0] in0,in1,in2,in3,in4,in5,in6,in7,in8,in9,in10,in11,in12,in13,in14,in15,in16,
in17,in18,in19,in20,in21,in22,in23,in24,in25,in26,in27,in28,in29,in30,in31;
input [4:0] addr;

always@(addr)
begin
case(addr)
5'd0:outd=in0;
5'd1:outd=in1;
5'd2:outd=in2;
5'd3:outd=in3;
5'd4:outd=in4;
5'd5:outd=in5;
5'd6:outd=in6;
5'd7:outd=in7;
5'd8:outd=in8;
5'd9:outd=in9;
5'd10:outd=in10;
5'd11:outd=in11;
5'd12:outd=in12;
5'd13:outd=in13;
5'd14:outd=in14;
5'd15:outd=in15;
5'd16:outd=in16;
5'd17:outd=in17;
5'd18:outd=in18;
5'd19:outd=in19;
5'd20:outd=in20;
5'd21:outd=in21;
5'd22:outd=in22;
5'd23:outd=in23;
5'd24:outd=in24;
5'd25:outd=in25;
5'd26:outd=in26;
5'd27:outd=in27;
5'd28:outd=in28;
5'd29:outd=in29;
5'd30:outd=in30;
5'd31:outd=in31;
default:outd=32'dz;
endcase
end
endmodule



module mem32x32(readdata1,readdata2,readaddr1,readaddr2,writedata,writeaddr,writeEn,clk,rst);

output [31:0] readdata1;
output [31:0] readdata2;
input [4:0] readaddr1;
input [4:0] readaddr2;
input [31:0] writedata;
input [4:0] writeaddr;
input writeEn;
input clk;
input rst;

wire [31:0] m0,m1,m2,m3,m4,m5,m6,m7,m8,m9,m10,m11,m12,m13,m14,m15,m16,
m17,m18,m19,m20,m21,m22,m23,m24,m25,m26,m27,m28,m29,m30,m31;

//decode 5 bit address to 32
wire [31:0] en;
assign en[0]=(~writeaddr[0])&(~writeaddr[1])&(~writeaddr[2])&(~writeaddr[3])&(~writeaddr[4])&writeEn,
en[1]=(writeaddr[0])&(~writeaddr[1])&(~writeaddr[2])&(~writeaddr[3])&(~writeaddr[4])&writeEn,
en[2]=(~writeaddr[0])&(writeaddr[1])&(~writeaddr[2])&(~writeaddr[3])&(~writeaddr[4])&writeEn,
en[3]=(writeaddr[0])&(writeaddr[1])&(~writeaddr[2])&(~writeaddr[3])&(~writeaddr[4])&writeEn,
en[4]=(~writeaddr[0])&(~writeaddr[1])&(writeaddr[2])&(~writeaddr[3])&(~writeaddr[4])&writeEn,
en[5]=(writeaddr[0])&(~writeaddr[1])&(writeaddr[2])&(~writeaddr[3])&(~writeaddr[4])&writeEn,
en[6]=(writeaddr[0])&(~writeaddr[1])&(writeaddr[2])&(~writeaddr[3])&(~writeaddr[4])&writeEn,
en[7]=(writeaddr[0])&(writeaddr[1])&(writeaddr[2])&(~writeaddr[3])&(~writeaddr[4])&writeEn,
en[8]=(~writeaddr[0])&(~writeaddr[1])&(~writeaddr[2])&(writeaddr[3])&(~writeaddr[4])&writeEn,
en[9]=(writeaddr[0])&(~writeaddr[1])&(~writeaddr[2])&(writeaddr[3])&(~writeaddr[4])&writeEn,
en[10]=(~writeaddr[0])&(writeaddr[1])&(~writeaddr[2])&(writeaddr[3])&(~writeaddr[4])&writeEn,
en[11]=(writeaddr[0])&(writeaddr[1])&(~writeaddr[2])&(writeaddr[3])&(~writeaddr[4])&writeEn,
en[12]=(~writeaddr[0])&(~writeaddr[1])&(writeaddr[2])&(writeaddr[3])&(~writeaddr[4])&writeEn,
en[13]=(writeaddr[0])&(~writeaddr[1])&(writeaddr[2])&(writeaddr[3])&(~writeaddr[4])&writeEn,
en[14]=(~writeaddr[0])&(writeaddr[1])&(writeaddr[2])&(writeaddr[3])&(~writeaddr[4])&writeEn,
en[15]=(writeaddr[0])&(writeaddr[1])&(writeaddr[2])&(writeaddr[3])&(~writeaddr[4])&writeEn,
en[16]=(~writeaddr[0])&(~writeaddr[1])&(~writeaddr[2])&(~writeaddr[3])&(writeaddr[4])&writeEn,
en[17]=(writeaddr[0])&(~writeaddr[1])&(~writeaddr[2])&(~writeaddr[3])&(writeaddr[4])&writeEn,
en[18]=(~writeaddr[0])&(writeaddr[1])&(~writeaddr[2])&(~writeaddr[3])&(writeaddr[4])&writeEn,
en[19]=(writeaddr[0])&(writeaddr[1])&(~writeaddr[2])&(~writeaddr[3])&(writeaddr[4])&writeEn,
en[20]=(~writeaddr[0])&(~writeaddr[1])&(writeaddr[2])&(~writeaddr[3])&(writeaddr[4])&writeEn,
en[21]=(writeaddr[0])&(~writeaddr[1])&(writeaddr[2])&(~writeaddr[3])&(writeaddr[4])&writeEn,
en[22]=(writeaddr[0])&(~writeaddr[1])&(writeaddr[2])&(~writeaddr[3])&(writeaddr[4])&writeEn,
en[23]=(writeaddr[0])&(writeaddr[1])&(writeaddr[2])&(~writeaddr[3])&(writeaddr[4])&writeEn,
en[24]=(~writeaddr[0])&(~writeaddr[1])&(~writeaddr[2])&(writeaddr[3])&(writeaddr[4])&writeEn,
en[25]=(writeaddr[0])&(~writeaddr[1])&(~writeaddr[2])&(writeaddr[3])&(writeaddr[4])&writeEn,
en[26]=(~writeaddr[0])&(writeaddr[1])&(~writeaddr[2])&(writeaddr[3])&(writeaddr[4])&writeEn,
en[27]=(writeaddr[0])&(writeaddr[1])&(~writeaddr[2])&(writeaddr[3])&(writeaddr[4])&writeEn,
en[28]=(~writeaddr[0])&(~writeaddr[1])&(writeaddr[2])&(writeaddr[3])&(writeaddr[4])&writeEn,
en[29]=(writeaddr[0])&(~writeaddr[1])&(writeaddr[2])&(writeaddr[3])&(writeaddr[4])&writeEn,
en[30]=(~writeaddr[0])&(writeaddr[1])&(writeaddr[2])&(writeaddr[3])&(writeaddr[4])&writeEn,
en[31]=(writeaddr[0])&(writeaddr[1])&(writeaddr[2])&(writeaddr[3])&(writeaddr[4])&writeEn;

mem1x32 mem0(m0,writedata,en[0],clk,rst);
mem1x32 mem1(m1,writedata,en[1],clk,rst);
mem1x32 mem2(m2,writedata,en[2],clk,rst);
mem1x32 mem3(m3,writedata,en[3],clk,rst);
mem1x32 mem4(m4,writedata,en[4],clk,rst);
mem1x32 mem5(m5,writedata,en[5],clk,rst);
mem1x32 mem6(m6,writedata,en[6],clk,rst);
mem1x32 mem7(m7,writedata,en[7],clk,rst);
mem1x32 mem8(m8,writedata,en[8],clk,rst);
mem1x32 mem9(m9,writedata,en[9],clk,rst);
mem1x32 mem10(m10,writedata,en[10],clk,rst);
mem1x32 mem11(m11,writedata,en[11],clk,rst);
mem1x32 mem12(m12,writedata,en[12],clk,rst);
mem1x32 mem13(m13,writedata,en[13],clk,rst);
mem1x32 mem14(m14,writedata,en[14],clk,rst);
mem1x32 mem15(m15,writedata,en[15],clk,rst);
mem1x32 mem16(m16,writedata,en[16],clk,rst);
mem1x32 mem17(m17,writedata,en[17],clk,rst);
mem1x32 mem18(m18,writedata,en[18],clk,rst);
mem1x32 mem19(m19,writedata,en[19],clk,rst);
mem1x32 mem20(m20,writedata,en[20],clk,rst);
mem1x32 mem21(m21,writedata,en[21],clk,rst);
mem1x32 mem22(m22,writedata,en[22],clk,rst);
mem1x32 mem23(m23,writedata,en[23],clk,rst);
mem1x32 mem24(m24,writedata,en[24],clk,rst);
mem1x32 mem25(m25,writedata,en[25],clk,rst);
mem1x32 mem26(m26,writedata,en[26],clk,rst);
mem1x32 mem27(m27,writedata,en[27],clk,rst);
mem1x32 mem28(m28,writedata,en[28],clk,rst);
mem1x32 mem29(m29,writedata,en[29],clk,rst);
mem1x32 mem30(m30,writedata,en[30],clk,rst);
mem1x32 mem31(m31,writedata,en[31],clk,rst);

mux32_1 mux0(readdata1,m0,m1,m2,m3,m4,m5,m6,m7,m8,m9,m10,m11,m12,m13,m14,m15,m16,
m17,m18,m19,m20,m21,m22,m23,m24,m25,m26,m27,m28,m29,m30,m31,readaddr1);
mux32_1 mux1(readdata2,m0,m1,m2,m3,m4,m5,m6,m7,m8,m9,m10,m11,m12,m13,m14,m15,m16,
m17,m18,m19,m20,m21,m22,m23,m24,m25,m26,m27,m28,m29,m30,m31,readaddr2);
endmodule