微信扫一扫1.0w+
社区成员
综合脚本教程,CIC Tapeout Review Form下载
Adding boundary condition :
input drive strength, input delay, output loading, output delay.
•Adding timing constraint :
specify clock, max delay, min delay
•Adding area constraint.
•Gate level code has no “assign”.
•Gate level code has no instance names named “cell”.
•Gate level code has no instanc
相关下载链接：//download.csdn.net/download/cuixiaodan/2209672?utm_source=bbsseo
input drive strength, input delay, output loading, output delay.
•Adding timing constraint :
specify clock, max delay, min delay
•Adding area constraint.
•Gate level code has no “assign”.
•Gate level code has no instance names named “cell”.
•Gate level code has no instanc
相关下载链接：//download.csdn.net/download/cuixiaodan/2209672?utm_source=bbsseo
...全文
当前发帖距今超过3年，不再开放新的回复
发表回复
综合脚本教程,CIC Tapeout Review Form Adding boundary condition : input drive strength, input delay, output loading, output delay. •Adding timing constraint : specify clock, max delay, min delay •Adding area constraint. ...
多级CIC滤波器的FPGA实现 CIC滤波器是一种高效的滤波器，广泛应用于软件无线电的数字上下变频端。介绍了CIC抽取滤波器基本原理...用Verilog HDL语言编写程序，实现该滤波器，通过MATLAB和Modelsim联合仿真，综合验证了设计的正确性和可行性。
CIC-IDS2018数据集 Friday-WorkingHours-Afternoon-DDos.pcap_ISCX.csv Friday-WorkingHours-Afternoon-PortScan.pcap_ISCX.csv Friday-WorkingHours-Morning.pcap_ISCX.csv Monday-WorkingHours.pcap_ISCX.csv Thursday-WorkingHours-...
CSE-CIC-IDS2018 加拿大入侵检测数据集 Wednesday数据 因为上传文件大小限制 Thuesday-20-02-2018_TrafficForML_CICFlowMeter.csv 不能上传，需要私信
pg140-cic-compiler.pdf vivado ip核 cic compilier的官方描述，感兴趣可以看看。The CIC Compiler core provides the ability to design and implement AXI4-Stream-compliant cascaded integrator-comb (CIC) filters.
Understanding_CIC_Compensation_Filters.pdf 该文档为CIC滤波器设计的经典文档。包括CIC滤波器原理介绍，以及设计准则建议。文中有不同抽取模式的验证，适合与不熟悉CIC补偿滤波器的同学使用。
