基于FPGA的自动售货机的程序，仿真程序及引脚怎么做？

[sjsjdb123]

module sell(yi_yuan,wu_jiao, get,half_out,sell_out,reset,clk);
parameter idle=0, half=1, one=2,two=3,three=4;
input yi_yuan,wu_jiao,reset,clk;
output get,half_out,sell_out;
reg get,half_out,sell_out;
reg[2:0] s;

always @(posedge clk)

begin
if(reset)
begin
sell_out=0; get=0; half_out=0; s=idle;
end
else
case(s)
idle: begin
sell_out=0; get=0; half_out=0;
if(wu_jiao) s=half;
else if(yi_yuan)s=one;
end
half: begin
if(wu_jiao) s=one;
else if(yi_yuan)
s=two;
end
one: begin
if(wu_jiao) s=two;
else if(yi_yuan)s=three;
end
two: begin
if(wu_jiao) s=three;
else if(yi_yuan)
begin
sell_out=1;get=1; s=idle;
end
end
three: begin
if(wu_jiao)
begin
sell_out=1; get=1; s=idle;
end
else if(yi_yuan)
begin
sell_out=1;get=1;half_out=1; s=idle;
end
end
default:begin
sell_out=0; get=0; half_out=0; s=idle;
end
endcase
end
endmodule

测试
`timescale 1ns/1ns
module sell_top;
reg yi_yuan,wu_jiao,reset,CLK;
wire get,half_out,sell_out;
always #50 CLK=~CLK;
initial
begin
CLK =0; reset=1;
#100 reset=0;
yi_yuan=0;
wu_jiao=0;
end

always@(posedge CLK)
begin
wu_jiao={$random}%2;#50 wu_jiao=0;
end
always@(posedge CLK)
begin
if(!wu_jiao)yi_yuan=1;#50 yi_yuan=0;
end
sell m(.yi_yuan(yi_yuan),.wu_jiao(wu_jiao), .get(get),
.half_out(half_out),.sell_out(sell_out),.reset(reset),.clk(CLK));
endmodule
这是我的程序和测试程序