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分享求助：FPGA 基于DDS信号发生器产生正弦，方波，锯齿波
头疼了老久编辑可以通过，但无法实现功能，相应mif ROM另生成。
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity XHFASH is
port(rst : in std_logic;
clk : in std_logic;
M,k0,p0: in std_logic; --模式，调频，移相位
quot: out std_logic_vector(7 downto 0));
end XHFASH ;
architecture arc of XHFASH is
signal clk1 : std_logic;
signal sel : std_logic_vector(1 downto 0):="00";
signal q_sin : std_logic_vector(7 downto 0); --sin信号
signal q_square : std_logic_vector(7 downto 0); --方波信号
signal q_sawtooth : std_logic_vector(7 downto 0); --锯齿波信号
signal counter,p1 : std_logic_vector(7 downto 0):="00000000";
signal k1 : std_logic_vector(7 downto 0):="00000001";
signal phase_shift: std_logic_vector(7 downto 0);
component sin --这是正弦波
port (
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component sin ;
component square--这是方波
port (
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component square ;
component sawtooth --这是锯齿波
port (
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component sawtooth;
begin
u1:sin port map(address=>phase_shift,q=>q_sin ,clock=>clk1);
u2:square port map(address=>phase_shift,q=>q_square,clock=>clk1);
u3:sawtooth port map(address=>phase_shift,q=>q_sawtooth,clock=>clk1);
process (clk)
variable n1:integer range 0 to 2;--1953
begin
if clk'event and clk='1' then
if n1= 2 then n1:=0;--1953
elsif n1< 2 then
n1:=n1+1;--1953
elsif n1> 1 then
clk1<='1';--977
else clk1<='0';
end if;
end if;
end process; --clk1=25600hz
process
begin
wait until clk1'event and clk1='1';
if rst='0' then
K1<="00000001";P1<="00000000";
end if;
if K0='0' then
elsif K1="00001010"
then K1<="00000001";
else
K1<=K1+1;
end if;
if P0='0' then
P1<=P1+16;
end if;
end process;
process
begin --累加器描述
wait until clk1'event and clk1='1';
if rst='0' then
counter<=(others=>'0');
else counter<=counter+K1;
end if;
end process;
--相位加法器描述
process
begin
wait until clk1'event and clk1='1';
if rst='0' then
phase_shift<=(others=>'0');
else phase_shift<=counter+p1;
end if;
end process;
--数据选择器；
process
begin
wait until clk1'event and clk1='1';
if M='0' then
elsif sel="10"
then sel<="00";
else
sel<=sel+1;
end if;
case sel is
when"00"=>quot<=q_sin ;
when"01"=>quot<=q_square;
when OTHERS=>quot<=q_sawtooth;
end case;
end process;
end arc;
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