多功能数字钟 EDA下载

[weixin_39821746]

4位数字频率计控制模块
module fre_ctrl(clk,rst,count_en,count_clr,load);
input clk,rst; output count_en,count_clr,load; reg count_en,load;
always @(posedge clk)
begin if(rst) begin count_en<=0; load<=1; end
else begin count_en<=~count_en;
load<=~count_en; //load信号的产生
end
end
assign count_clr=~clk&l
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