求教VHDL怎么实现倍频器

2019-06-18 11:15:23 1.1k 阅读 AI 写同款 · GEO 优化AI 选题数据监测一键分发 ›

基于VHDL语言分频器电路程序设计基于VHDL语言分频器电路程序设计（汇总）分频器简介：分频器是数字电路中最常用的电路之一，在 FPGA 的设计中也是使用效率非常高的基本设计。基于 FPGA 实现的分频电路一般有两种方法：一是使用FPGA 芯片内部提供的锁相环电路，如 ALTERA 提供的 PLL（Phase Locked Loop），Xilinx 提供的 DLL（Delay Locked Loop）；二是使用硬件描述语言，如VHDL、Verilog HDL 等。使用锁相环电路有许多优点，如可以实现倍频；相位偏移；占空比可调等。但 FP 阅读详情

我这里有一段代码，是输入50M时钟，输出100M时钟。
实在看不懂VHDL，想请教一下这段代码的大概意思。
主要是中间的CLK100 Generation的部分。



library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use ieee.math_real.All;



entity top is

	Port (

		CLK50			: in	std_logic;

		CLK100_o		:out	std_logic

	

		);

end top;



architecture Behavioral of top is



	-- CLOCK DCM Signals Definition

signal CLK100		: std_logic;

signal CLKTMP		: std_logic;

signal LOCKED		: std_logic							:= '0';

signal LOCK_CNT		: std_logic_vector(18 downto 0)		:= "000" & "00000000" & "00000001";

signal LOCK_STATUS	: std_logic_vector(7 downto 0)		:= "00000000";

signal RESET		: std_logic							:= '0';

signal RESET_DCM	: std_logic;

signal COUNT		: std_logic_vector(25 downto 0)		:= "00000000000000000000000000";



signal LED_SIGNAL1	: std_logic							:= '0';

signal LED_SIGNAL2	: std_logic							:= '1';

signal CARRIER			: std_logic_vector(25 downto 0)		:= "00000000000000000000000000";		

signal MODE				: std_logic							:= '1';

signal OPERATER		: std_logic_vector(25 downto 0)		:= "10011000100101101000000000";	--???10 0110 0010 0101 1010 0000 0000?





component BUFG

	port (

		I: in std_logic;

		O: out std_logic

		);

end component; 



component DCM is

	port (

		CLKFB		: in	std_logic;

		CLKIN		: in	std_logic;

		DSSEN		: in	std_logic;

		PSCLK		: in	std_logic;

		PSEN		: in	std_logic;

		PSINCDEC	: in	std_logic;

		RST		: in	std_logic;

		CLK0		: out	std_logic;

		CLK90		: out	std_logic;

		CLK180	: out	std_logic;



		CLK270	: out	std_logic;

		CLK2X		: out	std_logic;

		CLK2X180	: out	std_logic;

		CLKDV		: out	std_logic;

		CLKFX		: out	std_logic;

		CLKFX180	: out	std_logic;

		LOCKED	: out	std_logic;

		PSDONE	: out	std_logic;

		STATUS	: out	std_logic_vector(7 downto 0)

		);

end component;



attribute DFS_FREQUENCY_MODE		: string;

attribute CLKIN_PERIOD				: string;

attribute CLK_FEEDBACK				: string;

attribute CLKFX_MULTIPLY			: string;

attribute DFS_FREQUENCY_MODE of U2	: label is "LOW";

attribute CLKIN_PERIOD of U2		: label is "20";

attribute CLK_FEEDBACK of U2		: label is "NONE";

attribute CLKFX_MULTIPLY of U2		: label is "2";		-- for 100M clk



begin



	-- ========================

	-- CLK100 Generation

	-- ========================

	U2:DCM   port map( '0', CLK50, '0', '0', '0', '0', RESET_DCM, open, open, open,

						open, open, open,  open, CLKTMP, open, LOCKED, open, LOCK_STATUS ); 

	U3:BUFG  port map( CLKTMP, CLK100 );

	

	process(CLK50)

	begin

		if CLK50'event and CLK50 = '1' then

			if LOCKED = '1' and LOCK_STATUS(2) = '0' then

				LOCK_CNT <= "000" & "00000000" & "00000000";

				RESET_DCM <= '0';

			else

				LOCK_CNT <= LOCK_CNT + 1;

				if LOCK_CNT= "000" & "00000000" & "00000001" then

					RESET_DCM <= '1';

				else

					RESET_DCM <= '0';

				end if;

			end if;

		end if;

	end process;



	CLK100_o<=CLK100;

	





end Behavioral;