状态机

[zudongkonfzhituanli]

采用的系统时钟为50M,应该产生10us的高电平，为什么后面全是高电平？？？
module changshi3(u,pulse,clk,rst,huibao);
input clk,rst,pulse,u;？
output huibao;
reg huibao;
reg[3:0] state;
reg[31:0] cnt,cnt1,cnt2,cnt3;
parameter A='d0,B='d1,C='d2,D='d3,E='d4,F='d5,G='d6,H='d7;
always @(posedge clk or negedge rst)
if(!rst)
begin
state<=A;huibao<=0;cnt<=0;
cnt1<=0;cnt2<=0;
end
else
case(state)
A: begin if(u==0) state<=A;
else if(pulse)
state<=B;
else state<=A;end
B: begin if(u==0)state<=A;
else cnt<=cnt+1;
if(!pulse)
state<=C;
else
state<=B;end
C: begin if(u==0)state<=A;
else if(cnt>=124)
begin state<=D;cnt1<=cnt1+1;end
else state<=A;end
D: if(u==0) state<=A;
else if(pulse==0)
state<=D;
else state<=E;
E: if(u==0) state<=A;
else if(cnt1<2499)
state<=F;
else state<=A;
F: begin if(u==0) state<=A;
else cnt2<=cnt2+1;
if(pulse==1)
state<=F;
else
state<=G;end
G: if(cnt2>=124)
begin state<=H;huibao<=1;end
else state<=F;
H: if(cnt3==499)
begin
huibao<=0;state<=A;
end
else state<=G;
default:state<=A;
endcase
always @(posedge clk or negedge rst)
if(!rst)
cnt3<=0;
else if(huibao==1)
begin
if(cnt3==499)
cnt3<=0;
else begin cnt3<=cnt3+1;end end
endmodule