DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation.
The double data rate architecture is an 8n-prefetch architecture with an interface de-
signed to transfer two data words per clock cycle at the I/O pins. A single read or write
access consists of a single 8n-bit-wide, o
相关下载链接:
//download.csdn.net/download/fyb_jack/2831679?utm_source=bbsseo