ac-dc single stage data下载

weixin_39821746 2019-07-12 10:30:27
It is about AC-DC single stage DATA.
For LED application note.
相关下载链接：//download.csdn.net/download/carl616love/3101262?utm_source=bbsseo
...全文
10 回复 打赏 收藏 转发到动态 举报
写回复
用AI写文章
回复
切换为时间正序
请发表友善的回复…
发表回复
ac-dc single stage data
It is about AC-DC single stage DATA. For LED application note.
The Data Conversion Handbook
Chapter 1: Data Converter History ........................................................................................3 Section 1-1: Early History .............................................................................................................5 The Early Years: Telegraph to Telephone .......................................................................................... 6 The Invention of PCM ....................................................................................................................... 8 The Mathematical Foundations of PCM ........................................................................................... 9 The PCM Patents of Alec Harley Reeves ........................................................................................ 10 PCM and the Bell System: World War II through 1948 .................................................................. 11 Op Amps and Regenerative Repeaters: Vacuum Tubes to Solid-State ............................................ 13 Section 1-2: Data Converters of the 1950s and 1960s ...................................................................19 Commercial Data Converters: 1950s ............................................................................................... 19 Commercial Data Converter History: 1960s ................................................................................... 20 Data Converter Architectures .......................................................................................................... 23 Section 1-3: Data Converters of the 1970s ...................................................................................27 Monolithic Data Converters of the 1970s ........................................................................................28 Bipolar Process IC DACs of the 1970s ...........................................................................................28 CMOS IC DACs of the 1970s ......................................................................................................... 29 Monolithic ADCs of the 1970s ........................................................................................................ 31 Hybrid Data Converters of the 1970s .............................................................................................. 32 Modular Data Converters of the 1970s ............................................................................................ 35 Section 1-4: Data Converters of the 1980s ...................................................................................39 Monolithic DACs of the 1980s ........................................................................................................ 40 Monolithic ADCs of the 1980s ........................................................................................................ 41 Monolithic Flash ADCs of the 1980s .............................................................................................. 42 Hybrid and Modular DACs and ADCs of the 1980s ....................................................................... 42 Section 1-5: Data Converters of the 1990s ...................................................................................45 Monolithic DACs of the 1990s ........................................................................................................ 46 Monolithic ADCs of the 1990s ........................................................................................................ 48 Hybrid and Modular DACs and ADCs of the 1990s ....................................................................... 52 Section 1-6: Data Converters of the 2000s ...................................................................................53 Chapter 2: Fundamentals of Sampled Data Systems ...............................................................57 Section 2-1: Coding and Quantizing .............................................................................................57 Unipolar Codes ................................................................................................................................ 59 Gray Code ........................................................................................................................................ 61 Bipolar Codes .................................................................................................................................. 62 TLFeBOOKvi Contents Complementary Codes .................................................................................................................... 65 DAC and ADC Static Transfer Functions and DC Errors ............................................................... 66 Section 2-2: Sampling Theory ......................................................................................................73 The Need for a Sample-and-Hold Amplifi er (SHA) Function ........................................................ 74 The Nyquist Criteria ........................................................................................................................ 76 Baseband Antialiasing Filters .......................................................................................................... 78 Undersampling (Harmonic Sampling, Bandpass Sampling, IF Sampling, Direct IF-to-Digital Conversion) ................................................................................................. 80 Antialiasing Filters in Undersampling Applications ....................................................................... 81 Section 2-3: Data Converter AC Errors ........................................................................................83 Theoretical Quantization Noise of an Ideal N-Bit Converter .......................................................... 83 Noise in Practical ADCs .................................................................................................................. 88 Equivalent Input Referred Noise .................................................................................................... 89 Noise-Free (Flicker-Free) Code Resolution ................................................................................... 89 Dynamic Performance of Data Converters ...................................................................................... 90 Integral and Differential Nonlinearity Distortion Effects ................................................................ 90 Harmonic Distortion, Worst Harmonic, Total Harmonic Distortion (THD), Total Harmonic Distortion Plus Noise (THD + N) ...................................................................... 91 Signal-to-Noise-and-Distortion Ratio (SINAD), Signal-to-Noise Ratio (SNR), and Effective Number of Bits (ENOB) ....................................................................................... 91 Analog Bandwidth ........................................................................................................................... 92 Spurious Free Dynamic Range (SFDR) .......................................................................................... 93 Two-Tone Intermodulation Distortion (IMD) ................................................................................. 94 Second- and Third-Order Intercept Points, 1 dB Compression Point ............................................. 95 Multitone Spurious Free Dynamic Range ....................................................................................... 96 Wideband CDMA (WCDMA) Adjacent Channel Power Ratio (ACPR) and Adjacent Channel Leakage Ratio (ADLR) ................................................................................................. 97 Noise Power Ratio (NPR) ................................................................................................................ 98 Noise Factor (F) and Noise Figure (NF) ....................................................................................... 100 Aperture Time, Aperture Delay Time, and Aperture Jitter ........................................................... 106 A Simple Equation for the Total SNR of an ADC ........................................................................ 108 ADC Transient Response and Overvoltage Recovery ................................................................... 109 ADC Sparkle Codes, Metastable States, and Bit Error Rate (BER) ............................................. 111 DAC Dynamic Performance ......................................................................................................... 115 DAC Settling Time ................................................................................................................. 115 Glitch Impulse Area ............................................................................................................... 116 DAC SFDR and SNR ............................................................................................................. 117 Measuring DAC SNR with an Analog Spectrum Analyzer .................................................... 118 DAC Output Spectrum and sin (x)/x Frequency Roll-off ....................................................... 119 Oversampling Interpolating DACs ......................................................................................... 120 Section 2-4: General Data Converter Specifi cations ......................................................................123 Overall Considerations .................................................................................................................. 123 Logic Interface Issues .................................................................................................................... 124 Data Converter Logic: Timing and other Issues ............................................................................ 125 Section 2-5: Defi ning the Specifi cations .......................................................................................127 TLFeBOOKvii Contents Chapter 3: Data Converter Architectures ............................................................................147 Section 3-1: DAC Architectures .................................................................................................147 DAC Output Considerations .......................................................................................................... 148 Basic DAC Structures .................................................................................................................... 149 The Kelvin Divider (String DAC) .......................................................................................... 149 Thermometer (Fully-Decoded) DACs .................................................................................... 151 Binary-Weighted DACs .......................................................................................................... 153 R-2R DACs ............................................................................................................................. 155 Segmented DACs .................................................................................................................... 159 Oversampling Interpolating DACs ................................................................................................ 163 Multiplying DACs ......................................................................................................................... 164 Intentionally Nonlinear DACs ....................................................................................................... 164 Counting, Pulsewidth-Modulated (PWM) DACs .......................................................................... 167 Cyclic Serial DACs ........................................................................................................................ 167 Other Low Distortion Architectures .............................................................................................. 169 DAC Logic Considerations ............................................................................................................ 170 Section 3-2: ADC Architectures .................................................................................................175 The Comparator: A 1-Bit ADC ...................................................................................................... 178 High Speed ADC Architectures ..................................................................................................... 180 Flash Converters ..................................................................................................................... 180 Successive Approximation ADCs ........................................................................................... 185 Subranging, Error Corrected, and Pipelined ADCs ............................................................... 190 Serial Bit-Per-Stage Binary and Gray Coded (Folding) ADCs ............................................. 203 Counting and Integrating ADC Architectures ............................................................................... 211 A. H. Reeves’ 5-Bit Counting ADC ....................................................................................... 211 Charge Run-Down ADC ......................................................................................................... 212 Ramp Run-Up ADC ............................................................................................................... 212 Tracking ADC ........................................................................................................................ 213 Voltage-to-Frequency Converters (VFCs) .............................................................................. 214 Dual Slope/Multislope ADCs ................................................................................................. 218 Optical Converters ......................................................................................................................... 220 Resolver-to-Digital Converters (RDCs) and Synchros .................................................................. 221 Section 3-3: Sigma-Delta Converters ..........................................................................................231 Historical Perspective .................................................................................................................... 231 Sigma-Delta (Σ-∆) or Delta-Sigma (∆-Σ)? ................................................................................... 234 Basics of Sigma-Delta ADCs ........................................................................................................ 235 Idle Tone Considerations ............................................................................................................... 240 Higher Order Loop Considerations ............................................................................................... 241 Multibit Sigma-Delta Converters .................................................................................................. 242 Digital Filter Implications ............................................................................................................. 243 Multistage Noise Shaping (MASH) Sigma-Delta Converters ....................................................... 244 High Resolution Measurement Sigma-Delta ADCs ...................................................................... 245 Sigma-Delta DACs ........................................................................................................................ 249 Chapter 4: Data Converter Process Technology ....................................................................257 Section 4-1: Early Processes ......................................................................................................257 Vacuum Tube Data Converters ...................................................................................................... 257 TLFeBOOKviii Contents Solid State, Modular, and Hybrid Data Converters ....................................................................... 259 Calibration Processes ..................................................................................................................... 262 Section 4-2: Modern Processes ...................................................................................................265 Bipolar Processes ........................................................................................................................... 265 Thin Film Resistor Processes ........................................................................................................ 265 Complementary Bipolar (CB) Processes ....................................................................................... 266 CMOS Processes ........................................................................................................................... 266 Data Converter Processes and Architectures ................................................................................. 268 Section 4-3: Smart Partitioning .................................................................................................273 When Complete Integration Isn’t the Optimal Solution ................................................................ 273 Why Smart Partitioning is Necessary ........................................................................................... 276 What’s Changing? ......................................................................................................................... 277 Chapter 5: Testing Data Converters ...................................................................................283 Section 5-1: Testing DACs ........................................................................................................283 Static DAC Testing ........................................................................................................................ 283 End-Point Errors ..................................................................................................................... 284 Linearity Errors ...................................................................................................................... 286 Superposition and DAC Errors ............................................................................................... 286 Measuring DAC DNL and INL Using Superposition ............................................................ 287 Measuring DAC INL and DNL Where Superposition Does Not Hold .................................. 290 Testing DACs for Dynamic Performance ...................................................................................... 292 Settling Time .......................................................................................................................... 292 Glitch Impulse Area ............................................................................................................... 293 Oscilloscope Measurement of Settling Time and Glitch Impulse Area ................................ 294 Distortion Measurements ....................................................................................................... 295 Section 5-2: Testing ADCs ........................................................................................................303 A Brief Historical Overview of Data Converter Specifi cations and Testing ................................. 303 Static ADC Testing ........................................................................................................................ 304 Back-to-Back Static ADC Testing .......................................................................................... 306 Crossplot Measurements of ADC Linearity ........................................................................... 309 Servo-Loop Code Transition Test ........................................................................................... 310 Computer-Based Servo-Loop ADC Tester ............................................................................. 311 Histogram (Code Density) Test with Linear Ramp Input ...................................................... 312 Dynamic ADC Testing ................................................................................................................... 317 Manual “Back-to-Back” Dynamic ADC Testing ................................................................... 317 Measuring Effective Number of Bits (ENOB) Using Sinewave Curve Fitting ...................... 320 FFT Basics .............................................................................................................................. 322 FFT Test Setup Confi guration and Measurements ................................................................. 329 Verifying the FFT Accuracy ................................................................................................... 335 Generating Low Distortion Sinewave Inputs ......................................................................... 335 Noise Power Ratio (NPR) Testing .......................................................................................... 337 Measuring ADC Aperture Jitter Using the Locked-Histogram Test Method ......................... 338 Measuring Aperture Delay Time ............................................................................................ 340 Measuring ADC Aperture Jitter Using FFTs .......................................................................... 340 Measuring ADC Analog Bandwidth Using FFTs .................................................................. 342 Settling Time .......................................................................................................................... 343 TLFeBOOKix Contents Overvoltage Recovery Time ................................................................................................... 344 Video Testing, Differential Gain and Differential Phase ........................................................ 344 Bit Error Rate (BER) Tests ..................................................................................................... 348 Chapter 6: Interfacing to Data Converters ...........................................................................359 Section 6-1: Driving ADC Analog Inputs .....................................................................................359 Amplifer DC and AC Performance Considerations ...................................................................... 361 Rail-Rail Input Stages .................................................................................................................... 362 Output Stages ................................................................................................................................. 365 Gain and Level-Shifting Circuits Using Op Amps ........................................................................ 367 Op Amp AC Specifi cations and Data Converter Requirements .................................................... 369 Driving High Resolution Σ-∆ Measurement ADCs ....................................................................... 371 Driving Single-Ended Input Single-Supply 1.6 V to 3.6 V Successive Approximation ADCs ..... 372 Driving Single-Supply ADCs with Scaled Inputs ......................................................................... 373 Driving Differential Input CMOS Switched Capacitor ADCs ...................................................... 374 Single-Ended Drive Circuits for Differential Input CMOS ADCs ................................................ 376 Differential Input ADC Drivers ..................................................................................................... 378 Driving ADCs with Differential Amplifi ers .................................................................................. 382 Dual Op Amp Drivers .................................................................................................................... 383 Fully Integrated Differential Amplifi er Drivers ............................................................................. 384 Driving Differential Input ADCs with Integrated Differential Drivers ......................................... 387 Section 6-2: ADC and DAC Digital Interfaces(and Related Issues) ................................................397 Power-On Initialization of Data Converters ................................................................................. 397 Initialization of Data Converter Internal Control Registers ........................................................... 398 Low Power, Sleep, and Standby Modes ....................................................................................... 398 Single-Shot Mode, Burst Mode, and Minimum Sampling Frequency .......................................... 399 ADC Digital Output Interfaces ...................................................................................................... 400 ADC Serial Output Interfaces ....................................................................................................... 400 ADC Serial Interface to DSPs ...................................................................................................... 403 ADC Parallel Output Interfaces ..................................................................................................... 405 DAC Digital Input Interfaces ......................................................................................................... 408 DAC Serial Input Interfaces to DSPs ............................................................................................ 410 DAC Parallel Input Interfaces to DSPs .......................................................................................... 411 Section 6-3: Buffering DAC Analog Outputs ...............................................................................415 Differential to Single-Ended Conversion Techniques ................................................................... 416 Single-Ended Current-to-Voltage Conversion ............................................................................... 418 Differential Current-to-Differential Voltage Conversion ............................................................... 420 An Active Low-Pass Filter for Audio DAC .................................................................................. 420 Section 6-4: Data Converter Voltage References ..........................................................................423 Section 6-5: Sampling Clock Generation .....................................................................................427 Oscillator Phase Noise and Jitter ................................................................................................... 430 “Hybrid” Clock Generators ........................................................................................................... 437 Driving Differential Sampling Clock Inputs ................................................................................. 438 Sampling Clock Summary ............................................................................................................. 439 Chapter 7: Data Converter Support Circuits ........................................................................443 Section 7-1: Voltage References .................................................................................................443 Precision Voltage References ........................................................................................................ 443 TLFeBOOKx Contents Types of Voltage References .......................................................................................................... 444 Bandgap References ............................................................................................................... 446 Buried Zener References ........................................................................................................ 451 XFET References ................................................................................................................... 452 Voltage Reference Specifi cations .................................................................................................. 455 Tolerance ................................................................................................................................ 455 Drift ........................................................................................................................................ 455 Supply Range ......................................................................................................................... 456 Load Sensitivity ...................................................................................................................... 456 Line Sensitivity ....................................................................................................................... 457 Noise ....................................................................................................................................... 457 Scaled References .......................................................................................................................... 459 Voltage Reference Pulse Current Response ................................................................................... 460 Low Noise References for High Resolution Converters ............................................................... 462 Section 7-2: Low Dropout Linear Regulators ...............................................................................465 Linear Voltage Regulator Basics .................................................................................................... 465 Pass Devices and their Associated Trade Offs ............................................................................... 468 Low Dropout Regulator Architectures .......................................................................................... 472 The anyCAP Low Dropout Regulator Family ............................................................................... 475 Design Features Related to DC Performance ......................................................................... 475 Design Features Related to AC Performance ......................................................................... 476 A Basic Pole-Splitting Topology ............................................................................................ 477 The anyCAP Pole-Splitting Topology .................................................................................... 477 The anyCAP LDO series devices ........................................................................................... 478 Functional Diagram and Basic 50 mA LDO Regulator ......................................................... 479 LDO Regulator Thermal Considerations ............................................................................... 481 LDO Regulator Controllers ........................................................................................................... 485 Regulator Controller Differences ........................................................................................... 485 A Basic 5 V/1 A LDO Regulator Controller .......................................................................... 486 Selecting the Pass Device ....................................................................................................... 487 Thermal Design ...................................................................................................................... 488 Sensing Resistors for LDO Controllers .................................................................................. 489 PCB Layout Issues ................................................................................................................. 490 A 2.8 V/8 A LDO Regulator Controller ................................................................................. 491 Section 7-3: Analog Switches and Multiplexers ............................................................................493 CMOS Switch Basics .................................................................................................................... 494 Error Sources in the CMOS Switch ............................................................................................... 496 Applying the Analog Switch ........................................................................................................ 504 1 GHz CMOS Switches ................................................................................................................. 508 Video Switches and Multiplexers .................................................................................................. 508 Video Crosspoint Switches ............................................................................................................ 511 Digital Crosspoint Switches .......................................................................................................... 512 Switch and Multiplexer Families from Analog Devices ................................................................ 512 Parasitic Latchup in CMOS Switches and Muxes ......................................................................... 512 Section 7-4: Sample-and-Hold Circuits ........................................................................................519 Introduction and Historical Perspective ........................................................................................ 519 TLFeBOOKxi Contents Basic SHA Operation .................................................................................................................... 521 Track Mode Specifi cations ............................................................................................................ 522 Track-to-Hold Mode Specifi cations .............................................................................................. 522 Hold Mode Specifi cations ............................................................................................................. 526 Hold-to-Track Transition Specifi cations ....................................................................................... 528 SHA Architectures ......................................................................................................................... 529 Internal SHA Circuits for IC ADCs ............................................................................................... 531 SHA Applications .......................................................................................................................... 533 Chapter 8: Data Converter Applications .............................................................................539 Section 8-1: Precision Measurement and Sensor Conditioning ........................................................539 Applications of Precision Measurement Σ-∆ ADCs ...................................................................... 540 Weigh Scale Design Analysis Using the AD7730 ADC ................................................................ 544 Thermocouple Conditioning Using the AD7793 ........................................................................... 549 Direct Digital Temperature Measurements .................................................................................... 551 Microprocessor Substrate Temperature Sensors ............................................................................ 555 Applications of ADCs in Power Meters ........................................................................................ 558 Section 8-2: Multichannel Data Acquisition Systems .....................................................................563 Data Acquisition System Confi gurations ....................................................................................... 563 Multiplexing .................................................................................................................................. 564 Filtering Considerations in Data Acquisition Systems .................................................................. 567 Complete Data Acquisition Systems on a Chip ............................................................................. 568 Multiplexing Inputs to Σ-∆ ADCs ................................................................................................. 570 Simultaneous Sampling Systems ................................................................................................... 572 Data Distribution Systems ............................................................................................................ 574 Data Distribution Using an Infi nite Sample-and-Hold .................................................................. 578 Section 8-3: Digital Potentiometers ............................................................................................581 Modern Digital Potentiometers in Tiny Packages ......................................................................... 582 Digital Potentiometers with Nonvolatile Memory ........................................................................ 584 One-Time Programmable (OTP) Digital Potentiometers .............................................................. 585 Digital Potentiometer AC Considerations ..................................................................................... 586 Application Examples ................................................................................................................... 587 Section 8-4: Digital Audio .........................................................................................................591 Sampling Rate and THD + N Requirements for Digital Audio ..................................................... 592 Overall Trends in Digital Audio ADCs and DACs ........................................................................ 595 Voiceband Codecs .......................................................................................................................... 596 High Performance Audio ADCs and DACs in Separate Packages ................................................ 597 High Performance Multichannel Audio Codecs and DACs .......................................................... 600 Sample Rate Converters ................................................................................................................ 602 Section 8-5: Digital Video and Display Electronics .......................................................................607 Digital Video .................................................................................................................................. 607 Digital Video Formats ............................................................................................................ 608 Serial Data Interfaces ............................................................................................................. 612 Digital Video ADCs and DACs: Decoders, and Encoders ..................................................... 612 Specifi cations for Video Decoders and Encoders ................................................................... 614 Display Electronics ........................................................................................................................ 615 Flat Panel Display Electronics ............................................................................................... 619 TLFeBOOKxii Contents CCD Imaging Electronics ...................................................................................................... 622 Touchscreen Digitizers ........................................................................................................... 627 Section 8-6: Software Radio and IF Sampling ..............................................................................633 Evolution of Software Radio ......................................................................................................... 634 A Receiver Using Digital Processing at Baseband ........................................................................ 635 Narrowband IF-Sampling Digital Receivers ................................................................................. 636 Wideband IF-Sampling Digital Receivers ..................................................................................... 639 Increasing ADC Dynamic Range Using Dither ............................................................................. 649 Wideband Radio Transmitter Considerations ................................................................................ 655 Cellular Telephone Handsets ......................................................................................................... 659 The Role of ADCs and DACs in Cellular Telephone Handsets ..................................................... 661 SoftFone® and Othello Radio Chipsets from Analog Devices ..................................................... 662 Time-Interleaved IF Sampling ADCs with Digital Post-Processors ............................................. 667 Advanced Digital Post Processing ................................................................................................. 671 Advanced Filter Bank (AFB) ........................................................................................................ 672 AFB Design Example: The AD12400 12-Bit, 400 MSPS ADC ................................................... 673 Section 8-7: Direct Digital Synthesis (DDS) ................................................................................677 Introduction to DDS ...................................................................................................................... 677 Aliasing in DDS Systems .............................................................................................................. 681 Frequency Planning in DDS Systems ............................................................................................ 682 Modern Integrated DDS Systems .................................................................................................. 684 Section 8-8: Precision Analog Microcontrollers ............................................................................693 Characteristics of the MicroConverter Product Family ................................................................. 694 Some Σ-∆ MicroConverter Applications ....................................................................................... 700 ADuC7xxx MicroConverter Products Based on the ARM7 Processor Core ................................ 702 Chapter 9: Hardware Design Techniques .............................................................................709 Section 9-1: Passive Components ...............................................................................................711 Capacitors ...................................................................................................................................... 711 Dielectric Absorption ............................................................................................................. 712 Capacitor Parasitics and Dissipation Factor ........................................................................... 714 Tolerance, Temperature, and Other Effects ............................................................................ 715 Assemble Critical Components Last ...................................................................................... 715 Resistors and Potentiometers ......................................................................................................... 718 Resistor Parasitics ................................................................................................................... 720 Thermoelectric Effects ........................................................................................................... 720 Voltage Sensitivity, Failure Mechanisms, and Aging ............................................................. 722 Resistor Excess Noise ............................................................................................................ 723 Potentiometers ........................................................................................................................ 723 Inductance ...................................................................................................................................... 725 Stray Inductance ..................................................................................................................... 725 Mutual Inductance .................................................................................................................. 725 Ringing ................................................................................................................................... 728 Parasitic Effects in Inductors .................................................................................................. 728 Q or “Quality Factor” ............................................................................................................. 729 Don’t Overlook Anything .............................................................................................................. 729 TLFeBOOKxiii Contents Section 9-2: PC Board Design Issues ..........................................................................................733 Resistance of Conductors .............................................................................................................. 733 Voltage Drop in Signal Leads—“Kelvin” Feedback ..................................................................... 735 Signal Return Currents .................................................................................................................. 736 Grounding in Mixed Analog/Digital Systems ............................................................................... 737 Ground and Power Planes ...................................................................................................... 738 Double-Sided versus Multilayer Printed Circuit Boards ........................................................ 739 Multicard Mixed-Signal Systems ........................................................................................... 740 Separating Analog and Digital Grounds ................................................................................. 740 Grounding and Decoupling Mixed-Signal ICs with Low Digital Currents ........................... 742 Treat the ADC Digital Outputs with Care .............................................................................. 743 Sampling Clock Considerations ............................................................................................. 744 The Origins of the Confusion about Mixed-Signal Grounding: Applying Single-Card Grounding Concepts to Multicard Systems ...................................................................... 746 Summary: Grounding Mixed-Signal Devices with Low Digital Currents in a Multicard System ............................................................................................................... 747 Summary: Grounding Mixed-Signal Devices with High Digital Currents in a Multicard System ............................................................................................................... 748 Grounding DSPs with Internal Phase-Locked Loops ............................................................. 748 Grounding Summary .............................................................................................................. 749 Some General PC Board Layout Guidelines for Mixed-Signal Systems ...................................... 750 Skin Effect .............................................................................................................................. 751 Transmission Lines ................................................................................................................. 753 Be Careful With Ground Plane Breaks ................................................................................... 753 Ground Isolation Techniques .................................................................................................. 754 Static PCB Effects .................................................................................................................. 756 Sample MINIDIP and SOIC Op Amp PCB Guard Layouts .................................................. 758 Dynamic PCB Effects ............................................................................................................ 760 Stray Capacitance ................................................................................................................... 761 Capacitive Noise and Faraday Shields ................................................................................... 762 The Floating Shield Problem .................................................................................................. 762 Buffering ADCs Against Logic Noise ................................................................................... 763 Section 9-3: Analog Power Supply Systems ..................................................................................767 Linear IC Regulation ..................................................................................................................... 768 Some Linear Voltage Regulator Basics .................................................................................. 768 Pass Devices .......................................................................................................................... 770 ±15 V Regulator Using Adjustable Voltage ICs ..................................................................... 770 Low Dropout Regulator Architectures ................................................................................... 771 Fixed-Voltage, 50/100/200/500/1000/1500 mA LDO Regulators ......................................... 772 Adjustable Voltage, 200 mA LDO Regulator ......................................................................... 774 Charge-Pump Voltage Converters ................................................................................................. 775 Regulated Output Charge-Pump Voltage Converters .................................................................... 776 Linear Post Regulator for Switching Supplies .............................................................................. 778 Grounding Linear and Switching Regulators ................................................................................ 779 Power Supply Noise Reduction and Filtering ............................................................................... 782 Capacitors ............................................................................................................................... 782 TLFeBOOKxiv Contents Ferrites .................................................................................................................................... 786 Card Entry Filter ..................................................................................................................... 787 Rail Bypass/Distribution Filter ............................................................................................... 788 Local High Frequency Bypass/Decoupling ............................................................................ 789 Section 9-4: Overvoltage Protection ...........................................................................................793 In-Circuit Overvoltage Protection ................................................................................................. 793 General Input Common Mode Limitations ................................................................................... 793 Clamping Diode Leakage .............................................................................................................. 795 A Flexible Voltage Follower Protection Circuit ........................................................................... 796 Common-Mode Overvoltage Protection Using CMOS Channel Protectors ................................. 797 CM Overvoltage Protection Using High CM Voltage In Amp ...................................................... 798 Inverting Mode Op Amp Protection Schemes ............................................................................... 800 Amplifi er Output Voltage Phase-Reversal ..................................................................................... 800 An Output Phase-Reversal Do-it-Yourself Test ...................................................................... 802 Fixes for Output Phase–Reversal ........................................................................................... 802 Input Differential Protection ......................................................................................................... 803 Protecting In Amps Against Overvoltage ...................................................................................... 804 Overvoltage Protection Using CMOS Channel Protectors ............................................................ 808 Digital Isolators ............................................................................................................................. 810 Out-of-Circuit Overvoltage Protection .......................................................................................... 813 ESD Models and Testing ............................................................................................................... 817 Section 9-5: Thermal Management .............................................................................................823 Thermal Basics .............................................................................................................................. 823 Heat Sinking .................................................................................................................................. 825 Data Converter Thermal Considerations ....................................................................................... 829 Section 9-6: EMI/RFI Considerations .........................................................................................833 EMI/RFI Mechanisms ................................................................................................................... 834 EMI Noise Sources ........................................................................................................................ 834 EMI Coupling Paths ...................................................................................................................... 834 Noise Coupling Mechanisms ......................................................................................................... 834 Reducing Common-Impedance Noise ........................................................................................... 835 Noise Induced by Near-Field Interference .................................................................................... 836 Reducing Capacitance-Coupled Noise .......................................................................................... 836 Reducing Magnetically-Coupled Noise ........................................................................................ 837 Passive Components: Your Arsenal Against EMI .......................................................................... 838 Reducing System Susceptibility to EMI ........................................................................................ 839 A Review of Shielding Concepts ................................................................................................... 839 General Points on Cables and Shields ........................................................................................... 842 Input-Stage RFI Rectifi cation Sensitivity ...................................................................................... 846 Background: Op Amp and In Amp RFI Rectifi cation Sensitivity Tests ................................. 846 An Analytical Approach: BJT RFI Rectifi cation .................................................................... 847 An Analytical Approach: FET RFI Rectifi cation .................................................................. 848 Reducing RFI Rectifi cation Within Op amp and In Amp Circuits ......................................... 849 Op Amp Inputs ............................................................................................................................. 849 In Amp Inputs ................................................................................................................................ 850 Amplifi er Outputs and EMI/RFI ................................................................................................... 852 TLFeBOOKxv Contents Printed Circuit Board Design for EMI/RFI Protection .................................................................. 852 Choose Logic Devices Carefully .................................................................................................. 853 Design PCBs Thoughtfully ............................................................................................................ 853 Designing Controlled Impedances Traces on PCBs ..................................................................... 854 Microstrip PCB Transmission Lines ............................................................................................. 855 Some Microstrip Guidelines .......................................................................................................... 855 Symmetric Stripline PCB Transmission Lines .............................................................................. 856 Some Pros and Cons of Embedding Traces ................................................................................... 857 Dealing with High-Speed Logic .................................................................................................... 858 Section 9-7: Low Voltage Logic Interfacing ..................................................................................867 Voltage Tolerance and Voltage Compliance .................................................................................. 870 Interfacing 5 V Systems to 3.3 V Systems using NMOS FET “Bus Switches” ............................ 871 3.3 V/2.5 V Interfaces .................................................................................................................... 873 3.3 V/2.5 V, 3.3 V/1.8 V, 2.5 V/1.8 V Interfaces ............................................................................ 874 Hot Swap and Hot Plug Applications of Bus Switches ................................................................. 878 Internally Created Voltage Tolerance / Compliance ...................................................................... 879 Section 9-8: Breadboarding and Prototyping ...............................................................................881 “Deadbug” Prototyping ................................................................................................................. 882 Solder-Mount Prototyping ............................................................................................................. 884 Milled PCB Prototyping ................................................................................................................ 885 Beware of Sockets ......................................................................................................................... 886 Some Additional Prototyping Points ............................................................................................. 887 Evaluation Boards .......................................................................................................................... 887 General-Purpose Op Amp Evaluation Board from the Mid-1990s ........................................ 888 Dedicated Op Amp Evaluation Boards .................................................................................. 888 Data Converter Evaluation Boards ......................................................................................... 890 Index ...............................................................................................................................895
AD630锁相放大资料
a AD630 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved. REV. E Balanced Modulator/Demodulator FUNCTIONAL BLOCK DIAGRAM CM OFF ADJ CM OFF ADJ DIFF OFF ADJ DIFF OFF ADJ 6 5 4 3 2.5k AMP A 2.5k AMP B –V 10k 10k 17 5k 8 9 10 COMP 19 18 1 15 7 16 14 13 11 12 RINA CH A+ CH A– RINB CH B+ CH B– SEL B SEL A 2 20 COMP +VS VOUT RB RF RA CHANNEL STATUS B/A –VS AD630 A B PRODUCT DESCRIPTION The AD630 is a high precision balanced modulator that combines a flexible commutating architecture with the accuracy and temperature stability afforded by laser wafer trimmed thin film resistors. Its signal processing applications include balanced modulation and demodulation, synchronous detection, phase detection, quadrature detection, phase-sensitive detection, lock-in amplification, and square wave multiplication. A network of on-board applications resistors provides precision closed-loop gains of ±1 and ±2 with 0.05% accuracy (AD630B). These resistors may also be used to accurately configure multiplexer gains of +1, +2, +3, or +4. Alternatively, external feedback may be employed, allowing the designer to implement high gain or complex switched feedback topologies. The AD630 can be thought of as a precision op amp with two independent differential input stages and a precision comparator that is used to select the active front end. The rapid response time of this comparator coupled with the high slew rate and fast settling of the linear amplifiers minimize switching distortion. In addition, the AD630 has extremely low crosstalk between channels of –100 dB @ 10 kHz. The AD630 is used in precision signal processing and instrumentation applications that require wide dynamic range. When used as a synchronous demodulator in a lock-in amplifier configuration, it can recover a small signal from 100 dB of interfering noise (see Lock-In Amplifier Applications section). Although optimized for operation up to 1 kHz, the circuit is useful at frequencies up to several hundred kilohertz. Other features of the AD630 include pin programmable frequency compensation, optional input bias current compensation resistors, common-mode and differential-offset voltage adjustment, and a channel status output that indicates which of the two differential inputs is active. This device is now available to Standard Military Drawing (DESC) numbers 5962-8980701RA and 5962-89807012A. PRODUCT HIGHLIGHTS 1. The configuration of the AD630 makes it ideal for signal processing applications, such as balanced modulation and demodulation, lock-in amplification, phase detection, and square wave multiplication. 2. The application flexibility of the AD630 makes it the best choice for applications that require precisely fixed gain, switched gain, multiplexing, integrating-switching functions, and high speed precision amplification. 3. The 100 dB dynamic range of the AD630 exceeds that of any hybrid or IC balanced modulator/demodulator and is comparable to that of costly signal processing instruments. 4. The op amp format of the AD630 ensures easy implementation of high gain or complex switched feedback functions. The application resistors facilitate the implementation of most common applications with no additional parts. 5. The AD630 can be used as a 2-channel multiplexer with gains of +1, +2, +3, or +4. The channel separation of 100 dB @ 10 kHz approaches the limit achievable with an empty IC package. 6. The AD630 has pin strappable frequency compensation (no external capacitor required) for stable operation at unity gain without sacrificing dynamic performance at higher gains. 7. Laser trimming of comparator and amplifying channel offsets eliminates the need for external nulling in most cases. FEATURES Recovers Signal from 100 dB Noise 2 MHz Channel Bandwidth 45 V/s Slew Rate –120 dB Crosstalk @ 1 kHz Pin Programmable, Closed-Loop Gains of 1 and 2 0.05% Closed-Loop Gain Accuracy and Match 100 V Channel Offset Voltage (AD630BD) 350 kHz Full Power Bandwidth Chips Available 元器件交易网www.cecb2b.com –2– REV. E AD630–SPECIFICATIONS (@ 25C and VS = 15 V, unless otherwise noted.) AD630J/AD630A AD630K/AD630B AD630S Model Min Typ Max Min Typ Max Min Typ Max Unit GAIN Open-Loop Gain 90 110 100 120 90 110 dB ±1, ±2 Closed-Loop Gain Error 0.1 0.05 0.1 % Closed-Loop Gain Match 0.1 0.05 0.1 % Closed-Loop Gain Drift 2 2 2 ppm/°C CHANNEL INPUTS VIN Operational Limit1 (–VS + 4 V) to (+VS – 1 V) (–VS + 4 V) to (+VS – 1 V) (–VS + 4 V) to (+VS – 1 V) V Input Offset Voltage 500 100 500 μV Input Offset Voltage TMIN to TMAX 800 160 1000 μV Input Bias Current 100 300 100 300 100 300 nA Input Offset Current 10 50 10 50 10 50 nA Channel Separation @ 10 kHz 100 100 100 dB COMPARATOR VIN Operational Limit1 (–VS + 3 V) to (+VS – 1.5 V) (–VS + 3 V) to (+VS – 1.5 V) (–VS + 3 V) to (+VS – 1.3 V) V Switching Window ±1.5 ±1.5 ±1.5 mV Switching Window TMIN to TMAX ±2.0 ±2.0 ±2.5 mV Input Bias Current 100 300 100 300 100 300 nA Response Time (–5 mV to +5 mV Step) 200 200 200 ns Channel Status ISINK @ VOL = –VS + 0.4 V2 1.6 1.6 1.6 mA Pull-Up Voltage (–VS + 33 V) (–VS + 33 V) (–VS + 33 V) V DYNAMIC PERFORMANCE Unity Gain Bandwidth 2 2 2 MHz Slew Rate3 45 45 45 V/μs Settling Time to 0.1% (20 V Step) 3 3 3 μs OPERATING CHARACTERISTICS Common-Mode Rejection 85 105 90 110 90 110 dB Power Supply Rejection 90 110 90 110 90 110 dB Supply Voltage Range ±5 ±16.5 ±5 ±16.5 ±5 ±16.5 V Supply Current 4 5 4 5 4 5 mA OUTPUT VOLTAGE, @ RL = 2 kΩ TMIN to TMAX ±10 ±10 ±10 V Output Short-Circuit Current 25 25 25 mA TEMPERATURE RANGES Rated Performance–N Package 0 70 0 70 N/A °C Rated Performance–D Package –25 +85 –25 +85 –55 +125 °C NOTES 1If one terminal of each differential channel or comparator input is kept within these limits the other terminal may be taken to the positive supply. 2ISINK @ VOL = (–VS + 1); V is typically 4 mA. 3Pin 12 Open. Slew rate with Pin 12 and Pin 13 shorted is typically 35 V/μs. Specifications subject to change without notice. 元器件交易网www.cecb2b.com REV. E AD630 –3– THERMAL CHARACTERISTICS JC JA 20-Lead PDIP (N) 24°C/W 61°C/W 20-Lead Ceramic DIP (D) 35°C/W 120°C/W 20-Lead Leadless Chip Carrier LCC (E) 35°C/W 120°C/W 20-Lead SOIC (R-20) 38°C/W 75°C/W ABSOLUTE MAXIMUM RATINGS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 600 mW Output Short-Circuit to Ground . . . . . . . . . . . . . . . Indefinite Storage Temperature, Ceramic Package . . . –65°C to +150°C Storage Temperature, Plastic Package . . . . . –55°C to +125°C Lead Temperature Range (Soldering, 10 sec) . . . . . . . . 300°C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C PIN CONFIGURATIONS 20-Lead SOIC, PDIP, and CERDIP 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 TOP VIEW (Not to Scale) AD630 RINA RINB CH B+ CH B– CH A– CH A+ DIFF OFF ADJ DIFF OFF ADJ RB RF CM OFF ADJ RA CM OFF ADJ –VS SEL B SEL A +VS COMP VOUT CHANNEL STATUS B/A 20-Terminal CLCC 3 2 1 20 19 18 14 15 16 17 4 5 6 7 8 9 10 11 12 13 TOP VIEW (Not to Scale) AD630 DIFF OFF ADJ CM OFF ADJ CM OFF ADJ CHANNEL STATUS B/A –VS CH B+ RINB RA RF RB DIFF OFF ADJ CH A+ RIN A CH A– CH B– SEL B SEL A +VS COMP VOUT ORDERING GUIDE Model Temperature Ranges Package Description Package Option AD630JN 0°C to 70°C PDIP N-20 AD630KN 0°C to 70°C PDIP N-20 AD630AR –25°C to +85°C SOIC R-20 AD630AR-REEL –25°C to +85°C SOIC 13" Tape and Reel R-20 AD630AD –25°C to +85°C SBDIP D-20 AD630BD –25°C to +85°C SBDIP D-20 AD630SD –55°C to +125°C SBDIP D-20 AD630SD/883B –55°C to +125°C SBDIP D-20 5962-8980701RA –55°C to +125°C SBDIP D-20 AD630SE/883B –55°C to +125°C CLCC E-20A 5962-89807012A –55°C to +125°C CLCC E-20A AD630JCHIPS 0°C to 70°C Chip AD630SCHIPS –55°C to +125°C Chip CHIP METALLIZATION AND PINOUT Dimensions shown in inches and (millimeters). Contact factory for latest dimensions. CHIP AVAILABILITY The AD630 is available in laser trimmed, passivated chip form. The figure above shows the AD630 metallization pattern, bonding pads and dimensions. AD630 chips are available; consult factory for details. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD630 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. 元器件交易网www.cecb2b.com REV. E AD630 –4– 10 15 5 1 10 100 1k 10k 100k 1M RESISTIVE LOAD () CL = 100pF f = 1kHz CAP IN 5k VO 100pF RL Vi 5k OUTPUT VOLTAGE (V) 0 TPC 2. Output Voltage vs. Resistive Load INPUT VOLTAGE (V) dVO dt (V/s) 60 0 –60 –5 –3 –2 –1 1 4 40 20 –40 –20 –4 0 2 3 5 UNCOMPENSATED COMPENSATED TPC 5. dV dt O vs. Input Voltage 10 18 5 0 5 10 15 SUPPLY VOLTAGE (V) OUTPUT VOLTAGE (V) 15 5k 100pF Vi 5k 2k VO f = 1kHz CL = 100pF 0 TPC 3. Output Voltage Swing vs. Supply Voltage FREQUENCY (Hz) 120 60 0 100 1M 100 80 20 40 10 1k 10k 100k UNCOMPENSATED 10M 0 45 90 OPEN LOOP GAIN (dB) 135 180 COMPENSATED OPEN LOOP PHASE (C) 0 TPC 6. Gain and Phase vs. Frequency FREQUENCY (Hz) 15 10 5 1k 10k 100k 1M RL= 2k CL = 100pF 2k 5k 5k Vi VO 100pF OUTPUT VOLTAGE (V) 0 TPC 1. Output Voltage vs. Frequency FREQUENCY (Hz) COMMON-MODE REJECTION (dB) 120 60 0 1 10 100 1k 10k 100k 100 80 40 20 TPC 4. Common-Mode Rejection vs. Frequency AD630–Typical Performance Characteristics 元器件交易网www.cecb2b.com REV. E AD630 –5– 20mV 500ns 20mV 100 90 10 0% 20mV/DIV (Vo) 20mV/DIV (Vi) TOP TRACE: Vo BOTTOM TRACE: Vi 5k 10k 10k Vi CH A CH B 12 VO 2 20 19 18 13 9 10 14 16 15 TPC 7. Channel-to-Channel Switch-Settling Characteristic 100 90 10 0% 100mV 500ns 50mV 1mV 50mV/DIV (Vi) 1mV/DIV (A) TOP TRACE: Vi MIDDLE TRACE: SETTLING ERROR (A) BOTTOM TRACE: Vo 100mV/DIV (Vo) 12 CH A MIDDLE TRACE (A) 10k 10k VO BOTTOM TRACE TEKTRONIX 7A13 10k 1k 30pF 10k Vi TOP TRACE 2 20 13 14 15 TPC 8. Small Signal Noninverting Step Response 100 90 10 0% 10V 10V 1mV TOP TRACE: Vi MIDDLE TRACE: SETTLING ERROR (B) BOTTOM TRACE: Vo 5s 10V 20kHz (Vi) 1mV/DIV (B) 10V/DIV (Vo) 12 CH A 10k 10k VO BOTTOM TRACE 10k Vi TOP TRACE (B) MIDDLE TRACE 10k HP5082-2811 20 2 13 14 15 TPC 9. Large Signal Inverting Step Response 元器件交易网www.cecb2b.com REV. E AD630 –6– TWO WAYS TO LOOK AT THE AD630 The functional block diagram of the AD630 (see page 1) shows the pin connections of the internal functions. An alternative architectural diagram is shown in Figure 1. In this diagram, the individual A and B channel preamps, the switch, and the integrator output amplifier are combined in a single op amp. This amplifier has two differential input channels, only one of which is active at a time. 15 11 2 20 19 18 17 8 7 12 14 13 9 10 RA 5k 2.5k RF 10k 1 16 2.5k +VS RB 10k SEL B SEL A B/A A B –VS Figure 1. Architectural Block Diagram HOW THE AD630 WORKS The basic mode of operation of the AD630 may be easier to recognize as two fixed gain stages which can be inserted into the signal path under the control of a sensitive voltage comparator. When the circuit is switched between inverting and noninverting gain, it provides the basic modulation/demodulation function. The AD630 is unique in that it includes laser wafer trimmed thin-film feedback resistors on the monolithic chip. The configuration shown in Figure 2 yields a gain of ±2 and can be easily changed to ±1 by shifting RB from its ground connection to the output. The comparator selects one of the two input stages to complete an operational feedback connection around the AD630. The deselected input is off and has a negligible effect on the operation. A B RA 5k RF 10k VO RB 10k Vi 2 20 19 18 13 16 15 14 9 10 Figure 2. AD630 Symmetric Gain (±2) When Channel B is selected, the resistors RA and RF are connected for inverting feedback as shown in the inverting gain configuration diagram in Figure 3. The amplifier has sufficient loop gain to minimize the loading effect of RB at the virtual ground produced by the feedback connection. When the sign of the comparator input is reversed, Input B will be deselected and A will be selected. The new equivalent circuit will be the noninverting gain configuration shown in Figure 4. In this case, RA will appear across the op amp input terminals, but since the amplifier drives this difference voltage to zero, the closed-loop gain is unaffected. The two closed-loop gain magnitudes will be equal when RF/RA = 1 + RF/RB, which will result from making RA equal to RFRB/ (RF + RB) the parallel equivalent resistance of RF and RB. The 5 kΩ and the two 10 kΩ resistors on the AD630 chip can be used to make a gain of 2 as shown below. By paralleling the 10 kΩ resistors to make RF equal to 5 kΩ and omitting RB, the circuit can be programmed for a gain of ± 1 (as shown in Figure 9a). These and other configurations using the on-chip resistors present the inverting inputs with a 2.5 kΩ source impedance. The more complete AD630 diagrams show 2.5 kΩ resistors available at the noninverting inputs which can be conveniently used to minimize errors resulting from input bias currents. RA 5k RF 10k RB 10k Vi VO = – RF RA Vi Figure 3. Inverting Gain Configuration RA 5k RF 10k RB 10k Vi VO = (1+ RF RB ) Vi Figure 4. Noninverting Gain Configuration CIRCUIT DESCRIPTION The simplified schematic of the AD630 is shown in Figure 5. It has been subdivided into three major sections, the comparator, the two input stages, and the output integrator. The comparator consists of a front end made up of Q52 and Q53, a flip-flop load formed by Q3 and Q4, and two current steering switching cells Q28, Q29 and Q30, Q31. This structure is designed so that a differential input voltage greater than 1.5 mV in magnitude applied to the comparator inputs will completely select one of the switching cells. The sign of this input voltage determines which of the two switching cells is selected. 20 11 3 4 5 6 2 19 18 13 12 SEL A SEL B DIFF OFF ADJ DIFF OFF ADJ CM OFF ADJ CM OFF ADJ COMP Q74 Q44 CH A– CH A+ CH B+ CH B– i55 Q3 Q4 Q28 Q31 Q30 Q32 C122 C121 i22 i23 –VS VOUT i73 Q52 Q53 +VS Q65 Q33 Q34 Q62 Q35 Q36 Q67 Q70 Q24 Q25 Q29 10 9 8 Figure 5. AD630 Simplified Schematic 元器件交易网www.cecb2b.com REV. E AD630 –7– The collectors of each switching cell connect to an input transconductance stage. The selected cell conveys bias currents i22 and i23 to the input stage it controls, causing it to become active. The deselected cell blocks the bias to its input stage which, as a consequence, remains off. The structure of the transconductance stages is such that it presents a high impedance at its input terminals and draws no bias current when deselected. The deselected input does not interfere with the operation of the selected input ensuring maximum channel separation. Another feature of the input structure is that it enhances the slew rate of the circuit. The current output of the active stage follows a quasi-hyperbolic-sine relationship to the differential input voltage. This means that the greater the input voltage, the harder this stage will drive the output integrator, and the faster the output signal will move. This feature helps ensure rapid, symmetric settling when switching between inverting and noninverting closed loop configurations. The output section of the AD630 includes a current mirrorload (Q24 and Q25), an integrator-voltage gain stage (Q32), and a complementary output buffer (Q44 and Q74). The outputs of both transconductance stages are connected in parallel to the current mirror. Since the deselected input stage produces no output current and presents a high impedance at its outputs, there is no conflict. The current mirror translates the differential output current from the active input transconductance amplifier into single-ended form for the output integrator. The complementary output driver then buffers the integrator output to produce a low impedance output. OTHER GAIN CONFIGURATIONS Many applications require switched gains other than the ±1 and ±2 which the self-contained applications resistors provide. The AD630 can be readily programmed with three external resistors over a wide range of positive and negative gain by selecting and RB and RF to give the noninverting gain 1 + RF/RB and subsequent RA to give the desired inverting gain. Note that when the inverting magnitude equals the noninverting magnitude, the value of RA is found to be RBRF/(RB + RF). That is, RA should equal the parallel combination of RB and RF to match positive and negative gain. The feedback synthesis of the AD630 may also include reactive impedance. The gain magnitudes will match at all frequencies if the A impedance is made to equal the parallel combination of the B and F impedances. The same considerations apply to the AD630 as to conventional op amp feedback circuits. Virtually any function that can be realized with simple noninverting “L network” feedback can be used with the AD630. A common arrangement is shown in Figure 6. The low frequency gain of this circuit is 10. The response will have a pole (–3 dB) at a frequency f 1/(2 π 100 kΩC) and a zero (3 dB from the high frequency asymptote) at about 10 times this frequency. The 2 kΩ resistor in series with each capacitor mitigates the loading effect on circuitry driving this circuit, eliminates stability problems, and has a minor effect on the pole-zero locations. As a result of the reactive feedback, the high frequency components of the switched input signal will be transmitted at unity gain while the low frequency components will be amplified. This arrangement is useful in demodulators and lock-in amplifiers. It increases the circuit dynamic range when the modulation or interference is substantially larger than the desired signal amplitude. The output signal will contain the desired signal multiplied by the low frequency gain (which may be several hundred for large feedback ratios) with the switching signal and interference superimposed at unity gain. C –VS A B 10k VO 11.11k 12 Vi 100k 2k 2k C 2 20 19 18 13 7 8 9 10 SEL B SEL A CHANNEL STATUS B/A Figure 6. AD630 with External Feedback SWITCHED INPUT IMPEDANCE The noninverting mode of operation is a high input impedance configuration while the inverting mode is a low input impedance configuration. This means that the input impedance of the circuit undergoes an abrupt change as the gain is switched under control of the comparator. If gain is switched when the input signal is not zero, as it is in many practical cases, a transient will be delivered to the circuitry driving the AD630. In most applications, this will require the AD630 circuit to be driven by a low impedance source which remains “stiff ” at high frequencies. Generally, this will be a wideband buffer amplifier. FREQUENCY COMPENSATION The AD630 combines the convenience of internal frequency compensation with the flexibility of external compensation by means of an optional self-contained compensation capacitor. In gain of ±2 applications, the noise gain that must be addressed for stability purposes is actually 4. In this circumstance, the phase margin of the loop will be on the order of 60° without the optional compensation. This condition provides the maximum bandwidth and slew rate for closed loop gains of |2| and above. When the AD630 is used as a multiplexer, or in other configurations where one or both inputs are connected for unity gain feedback, the phase margin will be reduced to less than 20°. This may be acceptable in applications where fast slewing is a first priority, but the transient response will not be optimum. For these applications, the self-contained compensation capacitor may be added by connecting Pin 12 to Pin 13. This connection reduces the closed-loop bandwidth somewhat and improves the phase margin. For intermediate conditions, such as gain of ±1 where loop attenuation is 2, use of the compensation should be determined by whether bandwidth or settling response must be optimized. The optional compensation should also be used when the AD630 is driving capacitive loads or whenever conservative frequency compensation is desired. OFFSET VOLTAGE NULLING The offset voltages of both input stages and the comparator have been pretrimmed so that external trimming will only be required in the most demanding applications. The offset adjustment of the two input channels is accomplished by means of a differential and common-mode scheme. This facilitates fine adjustment of system errors in switched gain applications. With 元器件交易网www.cecb2b.com REV. E AD630 –8– the system input tied to 0 V, and a switching or carrier waveform applied to the comparator, a low level square wave will appear at the output. The differential offset adjustment potentiometers can be used to null the amplitude of this square wave (Pins 3 and 4). The common-mode offset adjustment can be used to zero the residual dc output voltage (Pins 5 and 6). These functions should be implemented using 10k trim potentiometers with wipers connected directly to Pin 8 as shown in Figures 9a and 9b. CHANNEL STATUS OUTPUT The channel status output, Pin 7, is an open collector output referenced to –VS that can be used to indicate which of the two input channels is active. The output will be active (pulled low) when Channel A is selected. This output can also be used to supply positive feedback around the comparator. This produces hysteresis which serves to increase noise immunity. Figure 7 shows an example of how hysteresis may be implemented. Note that the feedback signal is applied to the inverting (–) terminal of the comparator to achieve positive feedback. This is because the open collector channel status output inverts the output sense of the internal comparator. 1M 100k 100k –15V +5V 100 7 8 9 10 Figure 7. Comparator Hysteresis The channel status output may be interfaced with TTL inputs as shown in Figure 8. This circuit provides appropriate level shifting from the open-collector AD630 channel status output to TTL inputs. –15V +5V TTL INPUT AD630 +15V IN 914s 6.8k 22k 100k 2N2222 7 8 Figure 8. Channel Status—TTL Interface APPLICATIONS: BALANCED MODULATOR Perhaps the most commonly used configuration of the AD630 is the balanced modulator. The application resistors provide precise symmetric gains of ±1 and ±2. The ±1 arrangement is shown in Figure 9a and the ±2 arrangement is shown in Figure 9b. These cases differ only in the connection of the 10 kΩ feedback resistor (Pin 14) and the compensation capacitor (Pin 12). Note the use of the 2.5 kΩ bias current compensation resistors in these examples. These resistors perform the identical function in the ±1 gain case. Figure 10 demonstrates the performance of the AD630 when used to modulate a 100 kHz square wave carrier with a 10 kHz sinusoid. The result is the double sideband suppressed carrier waveform. These balanced modulator topologies accept two inputs, a signal (or modulation) input applied to the amplifying channels and a reference (or carrier) input applied to the comparator. MODULATED OUTPUT SIGNAL CARRIER INPUT CM ADJ DIFF ADJ 2.5k AMP A AMP B –V 10k 10k 5k 9 10 COMP 1 15 7 16 14 13 12 2 20 +VS –VS AD630 A 2.5k B 19 18 17 11 8 6 5 10k 4 3 10k MODULATION INPUT Figure 9a. AD630 Configured as a Gain-of-One Balanced Modulator MODULATED OUTPUT SIGNAL CARRIER INPUT CM ADJ DIFF ADJ 2.5k AMP A AMP B –V 10k 10k 5k 9 10 COMP 1 15 7 16 14 13 12 2 20 +VS –VS AD630 A 2.5k B 19 18 17 11 8 6 5 10k 4 3 10k MODULATION INPUT Figure 9b. AD630 Configured as a Gain-of-Two Balanced Modulator 10V 5V 5V 20s MODULATION INPUT CARRIER INPUT OUTPUT SIGNAL Figure 10. Gain-of-Two Balanced Modulator Sample Waveforms 元器件交易网www.cecb2b.com REV. E AD630 –9– BALANCED DEMODULATOR The balanced modulator topology described above will also act as a balanced demodulator if a double sideband suppressed carrier waveform is applied to the signal input and the carrier signal is applied to the reference input. The output under these circumstances will be the baseband modulation signal. Higher order carrier components that can be removed with a low-pass filter will also be present. Other names for this function are synchronous demodulation and phase-sensitive detection. PRECISION PHASE COMPARATOR The balanced modulator topologies of Figures 9a and 9b can also be used as precision phase comparators. In this case, an ac waveform of a particular frequency is applied to the signal input and a waveform of the same frequency is applied to the reference input. The dc level of the output (obtained by low-pass filtering) will be proportional to the signal amplitude and phase difference between the input signals. If the signal amplitude is held constant, the output can be used as a direct indication of the phase. When these input signals are 90° out of phase, they are said to be in quadrature and the AD630 dc output will be zero. PRECISION RECTIFIER ABSOLUTE VALUE If the input signal is used as its own reference in the balanced modulator topologies, the AD630 will act as a precision rectifier. The high frequency performance will be superior to that which can be achieved with diode feedback and op amps. There are no diode drops that the op amp must “leap over” with the commutating amplifier. LVDT SIGNAL CONDITIONER Many transducers function by modulating an ac carrier. A linear variable differential transformer (LVDT) is a transducer of this type. The amplitude of the output signal corresponds to core displacement. Figure 11 shows an accurate synchronous demodulation system which can be used to produce a dc voltage that corresponds to the LVDT core position. The inherent precision and temperature stability of the AD630 reduce demodulator drift to a second-order effect. A B 10k 10k 5k 2.5k 2.5k C 100k D 1F AD630 2 DEMODULATOR AD544 FOLLOWER B PHASE SHIFTER A E1000 SCHAEVITZ LVDT 2.5kHZ 2V p-p SINUSOIDAL EXCITATION 16 1 14 17 9 10 20 19 12 13 15 Figure 11. LVDT Signal Conditioner AC BRIDGE Bridge circuits that use dc excitation are often plagued by errors caused by thermocouple effects, 1/f noise, dc drifts in the electronics, and line noise pick-up. One way to get around these problems is to excite the bridge with an ac waveform, amplify the bridge output with an ac amplifier, and synchronously demodulate the resulting signal. The ac phase and amplitude information from the bridge is recovered as a dc signal at the output of the synchronous demodulator. The low frequency system noise, dc drifts, and demodulator noise all get mixed to the carrier frequency and can be removed by means of a low-pass filter. Dynamic response of the bridge must be traded off against the amount of attenuation required to adequately suppress these residual carrier components in the selection of the filter. Figure 12 is an example of an ac bridge system with the AD630 used as a synchronous demodulator. The bridge is excited by a 1 V 400 Hz excitation. Trace A in Figure 13 is the amplified bridge signal. Trace B is the output of the synchronous demodulator and Trace C is the filtered dc system output. AD8221 REF +IN –IN 49.9 350 350 350 350 CH B– SEL B CH A– SEL A RA RF RINA RINB –VS +15V VOUT +VS COMP AD630AR 12 13 1 8 RB 10 14 17 16 15 19 20 9 11 –15V 4.99k 4.99k 4.99k 2F 2F 2F A B C 1V 400Hz Figure 12. AC Bridge System 元器件交易网www.cecb2b.com REV. E AD630 –10– 500s/DIV B. 200mV/DIV C. 200mV/DIV 3 [ T ] T A. 200mV/DIV Figure 13. AC Bridge Waveforms (1 V Excitation) LOCK-IN AMPLIFIER APPLICATIONS Lock-in amplification is a technique used to separate a small, narrow-band signal from interfering noise. The lock-in amplifier acts as a detector and narrow-band filter combined. Very small signals can be detected in the presence of large amounts of uncorrelated noise when the frequency and phase of the desired signal are known. The lock-in amplifier is basically a synchronous demodulator followed by a low-pass filter. An important measure of performance in a lock-in amplifier is the dynamic range of its demodulator. The schematic diagram of a demonstration circuit which exhibits the dynamic range of an AD630 as it might be used in a lock-in amplifier is shown in Figure 14. Figure 15 is an oscilloscope photo demonstrating the large dynamic range of the AD630. The photo shows the recovery of a signal modulated at 400 Hz from a noise signal approximately 100,000 times larger. A B 10k 100R C OUTPUT LOW-PASS FILTER A B C R 100R AD630 10k 5k 2.5k 2.5k 20 19 17 1 16 AD542 13 AD542 14 10 9 CLIPPED BAND-LIMITED WHITE NOISE 100dB ATTENUATION 0.1Hz MODULATED 400Hz CARRIER CARRIER PHASE REFERENCE 15 Figure 14. Lock-In Amplifier 100 90 10 0% 5V 5V 5s 5mV MODULATED SIGNAL (A) (UNATTENUATED) ATTENUATED SIGNAL PLUS NOISE (B) OUTPUT Figure 15. Lock-In Amplifier Waveforms The test signal is produced by modulating a 400 Hz carrier with a 0.1 Hz sine wave. The signals produced, for example, by chopped radiation (i.e., IR, optical) detectors may have similar low frequency components. A sinusoidal modulation is used for clarity of illustration. This signal is produced by a circuit similar to Figure 9b and is shown in the upper trace of Figure 15. It is attenuated 100,000 times normalized to the output, B, of the summing amplifier. A noise signal that might represent, for example, background and detector noise in the chopped radiation case, is added to the modulated signal by the summing amplifier. This signal is simply band limited clipped white noise. Figure 15 shows the sum of attenuated signal plus noise in the center trace. This combined signal is demodulated synchronously using phase information derived from the modulator, and the result is low-pass filtered using a 2-pole simple filter which also provides a gain of 100 to the output. This recovered signal is the lower trace of Figure 15. The combined modulated signal and interfering noise used for this illustration is similar to the signals often requiring a lock-in amplifier for detection. The precision input performance of the AD630 provides more than 100 dB of signal range and its dynamic response permits it to be used with carrier frequencies more than two orders of magnitude higher than in this example. A more sophisticated low-pass output filter will aid in rejecting wider bandwidth interference. 元器件交易网www.cecb2b.com REV. E AD630 –11– OUTLINE DIMENSIONS 20-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] (D-20) Dimensions shown in inches and (millimeters) 20 1 10 11 0.300 (7.62) PIN 1 0.280 (7.11) 0.005 (0.13) MIN 0.080 (2.03) MAX SEATING PLANE 0.023 (0.58) 0.014 (0.36) 0.060 (1.52) 0.015 (0.38) 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.070 (1.78) 0.030 (0.76) 0.100 (2.54) BSC 0.150 (3.81) MIN 0.320 (8.13) 0.300 (7.62) 0.015 (0.38) 0.008 (0.20) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 1.060 (28.92) 0.990 (25.15) 20-Lead Plastic Dual In-Line Package [PDIP] (N-20) Dimensions shown in inches and (millimeters) 20 1 10 11 0.985 (25.02) 0.965 (24.51) 0.945 (24.00) 0.295 (7.49) 0.285 (7.24) 0.275 (6.99) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) SEATING PLANE 0.015 (0.38) MIN 0.180 (4.57) MAX 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.100 (2.54) BSC 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MO-095-AE 20-Terminal Ceramic Leadless Chip Carrier [LCC] (E-20A) Dimensions shown in inches and (millimeters) 1 20 4 9 8 13 19 14 3 18 BOTTOM VIEW 0.028 (0.71) 0.022 (0.56) 45 TYP 0.015 (0.38) MIN 0.055 (1.40) 0.045 (1.14) 0.050 (1.27) BSC 0.075 (1.91) REF 0.011 (0.28) 0.007 (0.18) R TYP 0.095 (2.41) 0.075 (1.90) 0.100 (2.54) REF 0.200 (5.08) REF 0.150 (3.81) BSC 0.075 (1.91) REF 0.358 (9.09) 0.342 (8.69) SQ 0.358 (9.09) MAX SQ 0.100 (2.54) 0.064 (1.63) 0.088 (2.24) 0.054 (1.37) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 元器件交易网www.cecb2b.com –12– REV. E C00784–0–6/04(E) Revision History Location Page 6/04—Data Sheet changed from REV. D to REV. E. Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Replaced Figure 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Changes to AC BRIDGE section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Replaced Figure 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Changes to LOCK-IN AMPLIFIER APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6/01—Data Sheet changed from REV. C to REV. D. Changes to SPECIFICATION TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Changes to PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Changes to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 20-Lead Standard Small Outline Package [SOIC] Wide Body (R-20) Dimensions shown in millimeters and (inches) CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MS-013AC 0.75 (0.0295) 0.25 (0.0098) 20 11 1 10 8 0 45 1.27 (0.0500) 0.40 (0.0157) SEATING PLANE 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) BSC 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 13.00 (0.5118) 12.60 (0.4961) COPLANARITY 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) AD630 元器件交易网www.cecb2b.com
Pre-IPL RAM Stage pseudo C code
Pre-IPL RAM Stage Dumped from Motherboard: TA-081 header file: /* * file: pre-IPL_ram_def.h * pre-IPL_ram pseudo C code * dumped from Motherboard: TA-081 */ #define ENDIAN_SWAP(_x) ((((_x)>8)
Lock-Free Data Structures
Lock-Free Data Structures By Andrei Alexandrescu, October 01, 2004 Post a Comment Lock-free data structures guarantee the progress of at least one thread when executing mutlithreaded procedures, th
下载资源悬赏专区

12,887

社区成员

12,439,057

社区内容

发帖
与我相关
我的任务
社区描述
CSDN 下载资源悬赏专区
其他 技术论坛（原bbs）
社区管理员
  • 下载资源悬赏专区社区
加入社区
  • 近7日
  • 近30日
  • 至今

加载中

查看更多榜单
社区公告
暂无公告

试试用AI创作助手写篇文章吧

+ 用AI写文章