请教,谁知道CardBus System Architecture 是个什么总线 ? [问题点数:20分]

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system architecture
hardware <em>architecture</em> design document
什么是企业服务总线
我们有个系统,是.net1.1做的,现在要接入到一个erp系统中,erp系统是采用soap等标准协议接入企业服务<em>总线</em>的,erp是j2ee的。rnrn现在erp系统要接入我们的系统,我们需要提供接口,说是提供服务注册到企业服务<em>总线</em>上,我们该如何了来做,是不是做些web service即可?
什么是sm总线
为<em>什么</em>装完系统以后这个出现了黄色的?rn是<em>什么</em>驱动没有装全码rnrn好像也没有影响<em>什么</em>啊?rnrn
System Idle Process是个什么进程?
System Idle Process是个<em>什么</em>进程?怎么偷偷的狂运行,要不是听到硬盘在响,我还不知道是怎么回事,一直在疯狂运行,到底它在干<em>什么</em>?
谁知道TTF160_TLB是个什么东东?
最近在编译一个别人写的很古老的程序时,因为它引用到一个叫做TTF160_TLB的文件,但又找不到那个文件,所以编译不通过,请各位达人指点,这是个派<em>什么</em>用场的东东,何处可以搞到?rn(这里面好像有个TF1Book6的class)rn
谁知道FlatBtn2.ocx是个什么控件?
给我发一个吧!急用!rnE-Mail:rnnicysun@263.net
PCI Express System Architecture
此书对pcie协议分析非常到位,简明清晰,是英文版,但非常值得一读!
Xbox 360 System Architecture
THIS ARTICLE COVERS THE XBOX 360’S HIGH-LEVEL TECHNICAL REQUIREMENTS, A SHORT SYSTEM OVERVIEW, AND DETAILS OF THE CPU AND THE GPU. THE AUTHORS DESCRIBE THEIR ARCHITECTURAL TRADE-OFFS AND SUMMARIZE THE SYSTEM’S SOFTWARE PROGRAMMING SUPPORT.
USB System Architecture(USB2.0)
USB System Architecture(USB2.0)pdf
PCI express system architecture
PCI express <em>system</em> <em>architecture</em>
USB System Architecture
USB System Architecture,mindshare publish,比spec容易理解
System Architecture with XML
System Architecture with XML
Architecture of a Database System
有关数据库系统的架构的讲解,书很薄,只有136页,用来作为知识入门吧。
PCI EXPRESS SYSTEM ARCHITECTURE
英文原始版,没有阉割的,读过中文翻译版,觉得还是英文原始版比较好一些,主要是和协议语言环境一致,翻译过的术语就有些奇怪了
80486 system architecture
英文版,详细介绍了80486处理器的架构。
IBM FileNet System and Architecture
This is the FileNet System and Architecture document.
computer system architecture
VIT Computer science专业 computer <em>system</em> <em>architecture</em> 课件
ISA System Architecture
ISA System Architecture
中文版
从数据库开发角度介绍数据库各个部件功能及彼此之间的关系
P6x System Architecture
Oracle P6x System Architecture
The Architecture of Computer Hardware, System
Understand <em>system</em> capabilities and limitations Create efficient application software for specific processing needs Specify computer <em>system</em>s and <em>architecture</em> to meet application requirements
ARM system on chip architecture
从别人那儿下的,没书签,自己加上的。 This book introduces the concepts and methodologies employed in designing a <em>system</em>-on-chip (SoC) based around a microprocessor core and in designing the microprocessor core itself. The principles of microprocessor design are made concrete by extensive illustrations based upon the ARM. The aim of the book is to assist the reader in understanding how SoCs and microprocessors are designed and used, and why a modern processor is designed the way that it is. The reader who wishes to know only the general principles should find that the ARM illustrations add substance to issues which can otherwise appear somewhat ethereal; the reader who wishes to understand the design of the ARM should find that the general principles illuminate the rationale for the ARM being as it is. Other microprocessor <em>architecture</em>s are not described in this book. The reader who wishes to make a comparative study of <em>architecture</em>s will find the required information on the ARM here but must look elsewhere for information on other designs.
pci system architecture
Introduction pci <em>system</em> <em>architecture</em>
EISA System Architecture
About This Book The MindShare Architecture Series.....................................................................................1 Organization of This Book.....................................................................................................2 Part One – The EISA Specification..................................................................................2 EISA Overview...........................................................................................................2 EISA Bus Structure Overview...................................................................................2 EISA Bus Arbitration..................................................................................................2 Interrupt Handling.....................................................................................................2 Detailed Description of EISA Bus.............................................................................3 ISA Bus Cycles............................................................................................................3 EISA CPU and Bus Master Bus Cycles....................................................................3 EISA DMA...................................................................................................................3 EISA System Configuration......................................................................................3 Part Two – The Intel 82350DT EISA Chipset.................................................................3 EISA System Buses.....................................................................................................3 Bridge, Translator, Pathfinder, Toolbox..................................................................3 Intel 82350DT EISA Chip Set....................................................................................4 Who This Book Is For..............................................................................................................4 Prerequisite Knowledge.........................................................................................................4 Documentation Conventions.................................................................................................4 Hex Notation......................................................................................................................5 Binary Notation..................................................................................................................5 Decimal Notation...............................................................................................................5 Signal Name Representation............................................................................................5 Bit Field Identification (logical bit or signal groups)....................................................5 We Want Your Feedback........................................................................................................6 Bulletin Board.....................................................................................................................6 Mailing Address................................................................................................................6 Part One – EISA Specification Chapter 1: EISA Overview Introduction..............................................................................................................................9 Compatibility With ISA.........................................................................................................10 Memory Capacity.....................................................................................................................10 v EISA System Architecture Synchronous Data Transfer Protocol...................................................................................10 Enhanced DMA Functions.....................................................................................................10 Bus Master Capabilities.........................................................................................................11 Data Bus Steering....................................................................................................................12 Bus Arbitration.........................................................................................................................12 Edge and Level-Sensitive Interrupt Requests....................................................................12 Automatic System Configuration.........................................................................................12 EISA Feature/Benefit Summary............................................................................................13 Chapter 2: EISA Bus Structure Overview Community of Processors.......................................................................................................15 Limitations of ISA Bus Master Support..........................................................................16 EISA Bus Master Support.................................................................................................17 EISA System Bus Master Types............................................................................................20 Types of Slaves in EISA System...........................................................................................21 Chapter 3: EISA Bus Arbitration EISA Bus Arbitration Scheme...............................................................................................23 Preemption................................................................................................................................28 Example Arbitration Between Two Bus Masters...............................................................29 Memory Refresh......................................................................................................................30 Chapter 4: Interrupt Handling ISA Interrupt Handling Review...........................................................................................33 ISA Interrupt Handling Shortcomings................................................................................34 Phantom Interrupts...........................................................................................................34 Limited Number of IRQ Lines.........................................................................................35 EISA Interrupt Handling........................................................................................................35 Shareable IRQ Lines..........................................................................................................35 Phantom Interrupt Elimination.......................................................................................40 Chapter 5: Detailed Description of EISA Bus Introduction..............................................................................................................................41 Address Bus Extension...........................................................................................................43 Data Bus Extension..................................................................................................................45 Bus Arbitration Signal Group...............................................................................................45 Burst Handshake Signal Group............................................................................................48 Bus Cycle Definition Signal Group.....................................................................................48 Bus Cycle Timing Signal Group...........................................................................................49 Lock Signal...............................................................................................................................49 Slave Size Signal Group.........................................................................................................50 AEN Signal...............................................................................................................................50 vi Contents EISA Connector Pinouts.........................................................................................................50 Chapter 6: ISA Bus Cycles Introduction..............................................................................................................................53 8-bit ISA Slave Device............................................................................................................53 16-bit ISA Slave Device..........................................................................................................54 Transfers With 8-bit Devices.................................................................................................54 Transfers With 16-bit Devices...............................................................................................57 Standard 16-bit Memory ISA bus Cycle.........................................................................58 Standard 16-bit I/O ISA bus Cycle.................................................................................61 Zero Wait State ISA bus Cycle Accessing 16-bit Device...............................................64 ISA DMA Bus Cycles..............................................................................................................67 ISA DMA Introduction.....................................................................................................67 8237 DMAC Bus Cycle......................................................................................................68 Chapter 7: EISA CPU and Bus Master Bus Cycles Intro to EISA CPU and Bus Master Bus Cycles..................................................................71 Standard EISA Bus Cycle.......................................................................................................72 General................................................................................................................................72 Analysis of EISA Standard Bus Cycle.............................................................................73 Performance Using EISA Standard Bus Cycle...............................................................75 Compressed Bus Cycle............................................................................................................75 General................................................................................................................................75 Performance Using Compressed Bus Cycle...................................................................76 Burst Bus Cycle........................................................................................................................77 General................................................................................................................................77 Analysis of EISA Burst Transfer......................................................................................77 Performance Using Burst Transfers................................................................................82 DRAM Memory Burst Transfers.....................................................................................82 Downshift Burst Bus Master............................................................................................82 Chapter 8: EISA DMA DMA Bus Cycle Types............................................................................................................83 Introduction........................................................................................................................83 Compatible DMA Bus Cycle............................................................................................84 Description..................................................................................................................84 Performance and Compatibility...............................................................................84 Type A DMA Bus Cycle....................................................................................................85 Description..................................................................................................................85 Performance and Compatibility...............................................................................85 Type B DMA Bus Cycle....................................................................................................86 Description..................................................................................................................86 vii EISA System Architecture Performance and Compatibility...............................................................................87 Type C DMA Bus Cycle....................................................................................................87 Description..................................................................................................................87 Performance and Compatibility...............................................................................87 EISA DMA Transfer Rate Summary...............................................................................88 Other DMA Enhancements....................................................................................................88 Addressing Capability......................................................................................................88 Preemption.........................................................................................................................89 Buffer Chaining..................................................................................................................89 Ring Buffers........................................................................................................................90 Transfer Size.......................................................................................................................90 Chapter 9: EISA System Configuration ISA I/O Address Space Problem...........................................................................................91 EISA Slot-Specific I/O Address Space.................................................................................94 EISA Product Identifier..........................................................................................................98 EISA Configuration Registers...............................................................................................100 Configuration Bits Defined by EISA Spec.........................................................................101 EISA Configuration Process..................................................................................................101 General................................................................................................................................101 Configuration File Naming..............................................................................................102 Configuration Procedure..................................................................................................103 Configuration File Macro Language...............................................................................104 Example Configuration File.............................................................................................104 Example File Explanation.................................................................................................110 Part Two – Intel 82350DT EISA Chipset Chapter 10: EISA System Buses Introduction..............................................................................................................................117 Host Bus.....................................................................................................................................118 EISA/ISA Bus...........................................................................................................................119 X-Bus..........................................................................................................................................119 Chapter 11: Bridge, Translator, Pathfinder, Toolbox Bus Cycle Initiation.................................................................................................................123 Bridge.........................................................................................................................................124 Translator..................................................................................................................................128 Address Translation..........................................................................................................128 Command Line Translation.............................................................................................128 Pathfinder..................................................................................................................................129 Toolbox......................................................................................................................................132 viii Contents Chapter 12: Intel 82350DT EISA Chipset Introduction..............................................................................................................................133 EISA Bus Controller (EBC) and EISA Bus Buffers (EBBs)...............................................134 General................................................................................................................................134 CPU Selection.....................................................................................................................135 Data Buffer Control and EISA Bus Buffer (EBB)...........................................................137 General.........................................................................................................................137 Transfer Between 32-bit EISA Bus Master and 8-bit ISA Slave............................139 Transfer Between 32-bit EISA Bus Master and 16-bit ISA Slave..........................145 Transfer Between 32-bit EISA Bus Master and 16-bit EISA Slave.......................150 Transfer Between 32-bit EISA Bus Master and 32-bit EISA Slave.......................153 Transfer Between 32-bit EISA Bus Master and 32-bit Host Slave........................155 Transfer Between 16-bit EISA Bus Master and 8-bit ISA Slave............................156 Transfer Between 16-bit EISA Bus Master and 16-bit ISA Slave..........................158 Transfer Between 16-bit EISA Bus Master and 16-bit EISA Slave.......................160 Transfer Between 16-bit EISA Bus Master and 32-bit EISA Slave.......................160 Transfer Between 16-bit ISA Bus Master and 8-bit ISA Slave..............................162 Transfer Between 16-bit ISA Bus Master and 16-bit ISA Slave............................162 Transfer Between 16-bit ISA Bus Master and 16-bit EISA Slave..........................163 Transfer Between 16-bit ISA Bus Master and 32-bit EISA Slave..........................164 Transfer Between 32-bit Host CPU and 32-bit Host Slave....................................165 Transfer Between 32-bit Host CPU and 8-bit ISA Slave........................................165 Transfer Between 32-bit Host CPU and 16-bit ISA Slave......................................166 Transfer Between 32-bit Host CPU and 16-bit EISA Slave...................................167 Transfer Between 32-bit Host CPU and 32-bit EISA Slave...................................167 Address Buffer Control and EBB.....................................................................................168 Host CPU Bus Master................................................................................................170 EISA Bus Master.........................................................................................................170 ISA Bus Master...........................................................................................................170 Refresh Bus Master.....................................................................................................171 DMA Bus Master........................................................................................................171 Host Bus Interface Unit.....................................................................................................172 ISA Bus Interface Unit.......................................................................................................176 EISA Bus Interface Unit....................................................................................................179 Cache Support....................................................................................................................180 Reset Control......................................................................................................................181 Slot-Specific I/O Support.................................................................................................181 Clock Generator Unit........................................................................................................181 I/O Recovery......................................................................................................................182 Testing.................................................................................................................................182 ISP interface unit................................................................................................................183 82357 Integrated System Peripheral (ISP)...........................................................................183 ix EISA System Architecture Introduction........................................................................................................................183 NMI Logic...........................................................................................................................185 Interrupt Controllers.........................................................................................................185 DMA Controllers...............................................................................................................186 System Timers....................................................................................................................187 Central Arbitration Control..............................................................................................188 Refresh Logic......................................................................................................................188 Miscellaneous Interface Signals.......................................................................................188 Glossary.....................................................................................................................................193 Index...........................................................................................................................................201
Entity system architecture with Unity
ECS这套系统在Unity下的应用,对于提高设计能力很有帮助
embedded system architecture
Book Description This comprehensive textbook provides a broad and in-depth overview of embedded <em>system</em>s <em>architecture</em> for engineering students and embedded <em>system</em>s professionals. The book is well-suited for undergraduate embedded <em>system</em>s courses in electronics/electrical engineering and engineering technology (EET) departments in universities and colleges, and for corporate training of employees. The book is a readable and practical guide covering embedded hardware, firmware, and applications. It clarifies all concepts with references to current embedded technology as it exists in the industry today, including many diagrams and applicable computer code. Among the topics covered in detail are: · hardware components, including processors, memory, buses, and I/O · <em>system</em> software, including device drivers and operating <em>system</em>s · use of assembly language and high-level languages such as C and Java · interfacing and networking · case studies of real-world embedded designs · applicable standards grouped by <em>system</em> application The CD-ROM accompanying the text contains source code for the design examples and numerous design tools useful to both students and professionals. A detailed laboratory manual suitable for a lab course in embedded <em>system</em>s design is also provided. Ancillaries also include a solutions manual and technical slides.
PCI Express system Architecture
PCI express 讲解的很好的一本书,如果看spec看不懂,可以先看看这个。
pci express system architecture
'We have always recommended these books to our customers and even our own engineers for developing a better understanding of technologies and specifications. We find the latest PCI Express book from MindShare to have the same content and high quality as all the others.' --Nader Saleh, CEO/President, Catalyst Enterprises, Inc. PCI Express is the third-generation Peripheral Component Inter-connect technology for a wide range of <em>system</em>s and peripheral devices. Incorporating recent advances in high-speed, point-to-point interconnect
什么是legacy system
我的理解就是原先的旧系统,心的设计需要在原先的旧系统基础上构造,不知道对不对
谁知道什么是ATL
水能给我讲讲,随便说一点
谁知道什么是XBase++ ?
<em>谁知道</em>,给介绍一下吧。rn另外 clipper怎么样?比foxbase好吗?
谁知道什么是~~~~~~~~~~~?
逆拓扑排序?????????rnrn网上有资料嘛???????
请问什么是服务总线
如题。<em>什么</em>服务<em>总线</em>?最好有详细的说明。
什么总线的驱动能力?
看到很多讲微机原理的书里都提到所谓的<em>总线</em>驱动能力,还有用8286数据收发器芯片可以增加<em>总线</em>的驱动能力,不知道该怎么理解。
什么是通用1#总线
<em>什么</em>是通用1#<em>总线</em>?<em>什么</em>是通用2#<em>总线</em>?比如三星ARM7 44B0是<em>什么</em>是通用1#<em>总线</em>还是<em>什么</em>是通用2#<em>总线</em>?
谁知道这是个什么芯片?
[img=https://img-bbs.csdn.net/upload/201810/22/1540192204_609306.png][/img]
GP TEE System Architecture v1.0
GlobalPlatform Device Technology TEE System Architecture Version 1.0
Mindshare: PCI Express System Architecture
Mindshare权威出版,完整英文原版(非扫描), 深入浅出,让你轻松掌握PCIe 协议。
NI TestStand System and Architecture Overview
NI TestStand System and Architecture Overview
An integrated approach to architecture and operating system
计算机系统系统架构与操作系统的高度集成
EISA System Architecture Second Edition
provides a detailed explanation of the isa enhancement as set forth in the eisa specification, and a detailed description of the features implemented by the intel 82350dt chip set.
Usb System Architecture (Usb 2.0)
Usb系统结构 Usb System Architecture
Computer System Architecture, 3rd Edition.pdf
Computer System Architecture, 3rd Edition.pdf
PCI Express System Architecture - 2003.chm
PCI 系统结构 英文版,只要一个文件。帮助你看最标准的描述。
PCI Express System Architecture完整版
Addison.Wesley.PCI.Express.System.Architecture.eBook-LiB 完整版
PCI System Architecture (4th Edition)
PCI System Architecture (4th Edition)
Overview Of The GSM System and Protocol Architecture
Overview Of The GSM System and Protocol Architecture
Computer System Architecture (3rd Edition)
《计算机体系结构》第三版 英文原版教材 作者M.Morris Mano
ISA系统架构 <>
ISA 系统架构,好东西,识货来拿.如果想了解计算机历史,想从底层弄清楚PC架构,这本书是值得一看的,强烈推荐.
PCI System Architecture 4th Edition.rar
PCI System Architecture 4th Edition.rar
什么是系统负载,System Load
System Load,系统负载,指当前正在被CPU执行和等待被CPU执行的进程数目总和,是反映系统忙闲程度的重要指标。 多核CPU情况下,完美情况是所有CPU都在使用,没有进程在等待处理,所以,load的理想值是CPU的数目。 当load值低于CPU数目时,表示CPU有空闲,资源存在浪费;当load值高于CPU数目时,表示进程在排队等待CPU,表示系统资源不足,影响应用程序的执行性能。...
谁知道rbeacon是个什么东西?
公司要进行JSP到DBMS的看法,中间用rbeacon做XML转化,有哪位高手知道如何取得rbeacon和安装(windows 平台)。
IEEE 1394 Cardbus controller 是身麼
IEEE 1394 Cardbus controller 是身麼
谁知道什么是“菊花链”现象
大概是说在一个网段中若存在三台以上的hub,会造成网络中断。知道详情的请告诉我。
谁知道什么是容器么?
如题。
谁知道什么是 增量查询 ?
-
谁知道什么是Glue Code?
In programming, glue code is code that does not contribute any functionality towards meeting the program's requirements, but instead serves solely to "glue together" different parts of code that would not otherwise be compatible. Glue code often appears in code written to let existing libraries or programs interoperate, as in foreign function interfaces like the Java native interface, or when mapping objects to a database using Object-Relational Mapping, or when integrating two or more Commercial off-the-shelf programs.rnrn在wiki是找到对glue code的定义,但看不懂。谁帮我翻译一下?在《Mastering Enterprise JavaBeans 3.0》中看到的关键词。
谁知道什么是程序测试
能给些网址吗?
谁知道什么是'银行家算法‘啊!!
-
谁知道什么是软件IS模型?
我们的 “CEO”又给我出难题了,<em>什么</em>是软件IS模型?rn我水平太臭我只知道有业务模型,数据模型... 没听过有<em>什么</em>IS模型呀
谁知道system相关的函数
除了<em>system</em>("cls")和<em>system</em>("pause");rn其它还有些<em>什么</em>?rn在MSDN上怎么也找不到..
请教,codeWright是个什么软件
codeWright 是第三方IDE吗?rn哪里有它的破解版本或注册机,rn最好发到我的信箱gqyeagle@vip.citiz.net(给5分)rn谢谢!!!
请教同步422是个什么东东?
<em>请教</em>同步422是个<em>什么</em>东东?
请教!SVCHOST。EXE是个什么程序?
这玩意在任务管理器的进程中是我能看见三个,并且我没法关闭它。rn另外,现在每天开机,机器都自动检测系统分区C:,老有文件报错,怪了,以前没有出现过这样的问题啊。
请教:oracle的回滚段是个什么概念?
谁能简要介绍一下回滚段的概念和作用。谢谢!
请教IEWebControls 是个什么东东?
<em>请教</em>IEWebControls 是个<em>什么</em>东东?又<em>什么</em>用处,谢谢。
各位大虾谁能给我个《plug and play system architecture》?非常感谢
各位大虾谁能给我个《plug and play <em>system</em> <em>architecture</em>》?非常感谢, 我的邮箱jerk66@163.com
请问System Idle Process是个什么进程???
如题??具体是做<em>什么</em>的,可以关了吗???为<em>什么</em>狂占CPU哦?谢了
Syba eSATA Cardbus Driver
用于西霸<em>cardbus</em>-eSATA 卡的driver
pcmcia cardbus 协议
PC卡协议标准,包括CARDBUS,比较完整。
谁知道 Encountered an improper argument 是个什么错误?怎么解决?
刚刚入门SQL,在网上搜的mfc链接SQL数据库,用CDatabase 和CRecordset 类,我在APP.CPP里谢了一个函数,用来对比用户密码,当我第一次调用这个函数是是正常的,但是第二次调用时就弹出Encountered an improper argument 这个错误,[code=c]BOOL CMyServerApp::Login(CString name, CString pass)rnrn CString st1 = _T("SELECT mima FROM dbo.卖家账户信息 WHERE SNo=")+name;rn CString st2=NULL;rn TRYrn rn rs.Open(AFX_DB_USE_DEFAULT_TYPE,st1); //打开查询记录rn rs.GetFieldValue(_T("mima"),st2); //得到数据 rn rn CATCH(CDBException,ex)rn rn AfxMessageBox(ex->m_strError);rn AfxMessageBox(ex->m_strStateNativeOrigin);rn rn AND_CATCH(CMemoryException,pEx)rn rn pEx->ReportError();rn AfxMessageBox(_T("memory exception"));rn rn END_CATCHrnrn if(st2==pass)rn rn return true;rn rn elsern rn return false;rn rnrn[/code]rnrn我是用这个方法链接的SQL数据库 http://blog.csdn.net/ljinddlj/article/details/1793544
小弟初学vc,谁知道PCH文件是个什么文件啊?
每次编译都是这样的提示:fatal error C1083: Cannot open precompiled header file: 'Debug/1.pch': No such file or directory,1是我的工程名,请各位提示.
谁知道win98任务栏右侧的托盘是个什么类?
我知道Win2000的托盘是个CToolBarCtrl,但是Win98好象不是。
谁知道微软的Windows SharePoint Portal是个什么技术啊?
<em>谁知道</em>微软的Windows SharePoint Portal是个<em>什么</em>技术啊? 望指点!!
大家帮帮忙,什么是I2S总线
可别看成是I2C<em>总线</em>啊。
总线隔离是一个什么概念?
对于多个单片机,无主从和有主从,分别该怎么解决?
MoreSQL是个什么
MoreSQL是像NoSQL那样是一种理念?还是像MySQL那样是一种MoreSQL理念的产品实现?
windows.net是个什么
看到有下载是<em>什么</em>了?
背景色换肤实例.rar下载
cookie的使用,动态改变背景色,并进行保存! 相关下载链接:[url=//download.csdn.net/download/zb312022948/2226228?utm_source=bbsseo]//download.csdn.net/download/zb312022948/2226228?utm_source=bbsseo[/url]
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绚丽的图片预览,国外高品质网站代码。 适用各种浏览器,JS实现,强烈推荐,倾情奉献!!!! 相关下载链接:[url=//download.csdn.net/download/dreamlearner2011/3827727?utm_source=bbsseo]//download.csdn.net/download/dreamlearner2011/3827727?utm_source=bbsseo[/url]
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我们是很有底线的