锁相环解码 verilog语言
if(~reset)
begin
counter <= 0;
m_clk <= 0;
end
else
begin
counter <= counter + 1;
if(counter == counter_L)
begin
m_clk <= 1;
end
else if(counter == counter_H)
begin
m_clk <= 0;
counter <= 0;
end
end
end
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