DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation.
The double data rate architecture is an 8n-prefetch architecture with an interface de-
signed to transfer two data words per clock cycle at the I/O pins. A single read or write
access consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal
DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at
the I/O pins.