verilog hdl代码帮忙给看看是哪里有错

游戏属性修改器 2020-05-10 06:13:20
这个是一个密码锁的密码模块,但是我键盘输入的键值无法进入,我仿真时键盘输入了准备值(13),然后输入了数字,但是四个密码的寄存器就是不变,有没有大神帮忙看看

module admin(clk,key,p0,p1,p2,p3,boom,error,flag);

input clk;
input [3:0] key;//按键输入
input flag;

output reg [3:0] p0,p1,p2,p3;//密码暂存
output reg boom,error;

parameter idle= 4'b0000;
parameter s0= 4'b0001;
parameter s1= 4'b0010;
parameter s2= 4'b0011;
parameter s3= 4'b0100;
parameter check= 4'b0101;
parameter boom0= 4'b0110;
parameter error0= 4'b0111;
parameter change0= 4'b1000;
parameter change1= 4'b1001;
parameter change2= 4'b1010;
parameter change3= 4'b1011;
parameter check0= 4'b1100;

reg [3:0] m0,m1,m2,m3;//老密码


reg[3:0] next_state;//次态
reg[3:0] current_state;//现态
reg set;//设定密码表示位
reg [12:0] cnt;

always@(posedge clk)
begin
current_state<=next_state;
end


always@(posedge clk)
begin
case(current_state)
idle://等待
begin
if(key==13)//准备
begin
next_state<=s0;
end
else
begin
next_state<=idle;
end
if(key==10)//设定密码
begin
set<=1;
next_state<=s0;
end
else
begin
next_state<=idle;
end
end
s0://第一位密码
begin
if(key==0||key==1||key==2||key==3||key==4||key==5||key==6||key==7||key==8||key==9)//键盘数字键输入标志
begin
p0<=key;
next_state<=s1;
end
else
begin
next_state<=s0;
end
end
s1://第二位密码
begin
if(key==0||key==1||key==2||key==3||key==4||key==5||key==6||key==7||key==8||key==9)
begin
p1<=key;
next_state<=s2;
end
else
begin
next_state<=s1;
end
if(key==11)//退格
begin
p0<=4'b0000;
next_state<=s0;
end
else
begin
next_state<=s1;
end
end
s2:
begin
if(key==0||key==1||key==2||key==3||key==4||key==5||key==6||key==7||key==8||key==9)
begin
p2<=key;
next_state<=s3;
end
else
begin
next_state<=s2;
end
if(key==11)
begin
p1<=4'b0000;
next_state<=s1;
end
else
begin
next_state<=s2;
end
end
s3:
begin
if(key==0||key==1||key==2||key==3||key==4||key==5||key==6||key==7||key==8||key==9)
begin
p3<=key;
next_state<=check;
end
else
begin
next_state<=s3;
end
if(key==11)
begin
p2<=4'b0000;
next_state<=s2;
end
else
begin
next_state<=s3;
end
end
check://密码检查
begin
if(key==11)
begin
p3<=4'b0000;
next_state<=s3;
end
else
begin
next_state<=check;
end
if(key==14)
begin
if(m3==p3&&m2==p2&&m1==p1&&m0==p0)
begin
if(set==1)//进入密码设定
begin
next_state<=change0;
p0<=4'b0000;
p1<=4'b0000;
p2<=4'b0000;
p3<=4'b0000;
set<=0;
end
if(set==0)//不进入密码设定
begin
next_state<=boom0;
p0<=4'b0000;
p1<=4'b0000;
p2<=4'b0000;
p3<=4'b0000;
end
end
else//密码错了
begin
next_state<=error0;
p0<=4'b0000;
p1<=4'b0000;
p2<=4'b0000;
p3<=4'b0000;
end
end
else
begin
next_state<=check;
end
end
change0://设定密码第一位
begin
if(key==0||key==1||key==2||key==3||key==4||key==5||key==6||key==7||key==8||key==9)
begin
p0<=key;
next_state<=change1;
end
else
begin
next_state<=change0;
end
end
change1:
begin
if(key==0||key==1||key==2||key==3||key==4||key==5||key==6||key==7||key==8||key==9)
begin
p1<=key;
next_state<=change2;
end
else
begin
next_state<=change1;
end
if(key==11)
begin
p0<=4'b0000;
next_state<=change0;
end
else
begin
next_state<=change1;
end
end
change2:
begin
if(key==0||key==1||key==2||key==3||key==4||key==5||key==6||key==7||key==8||key==9)
begin
p2<=key;
next_state<=change3;
end
else
begin
next_state<=change2;
end
if(key==11)
begin
p1<=4'b0000;
next_state<=change1;
end
else
begin
next_state<=change2;
end
end
change3:
begin
if(key==0||key==1||key==2||key==3||key==4||key==5||key==6||key==7||key==8||key==9)
begin
p3<=key;
next_state<=check0;
end
else
begin
next_state<=change3;
end
if(key==11)
begin
p2<=4'b0000;
next_state<=change2;
end
else
begin
next_state<=change3;
end
end
check0:
begin
if(key==11)
begin
p3<=4'b0000;
next_state<=change3;
end
else
begin
next_state<=check0;
end
if(key==14)//确定,赋给原密码
begin
m3<=p3;
m2<=p2;
m1<=p1;
m0<=p0;

p0<=4'b0000;
p1<=4'b0000;
p2<=4'b0000;
p3<=4'b0000;

next_state<=idle;
end
else
begin
next_state<=check0;
end
end
boom0://爆炸预警
begin
if(cnt<5000)
begin
boom<=1;
cnt<=cnt+1;
next_state<=boom0;

end
else
begin
boom<=0;
cnt<=0;
next_state<=idle;
end
end
error0://错误预警
begin
if(key==12)
begin
error<=0;
next_state<=idle;
end
else
begin
error<=1;
next_state<=error0;
end
end
endcase
end



endmodule






...全文
68 3 打赏 收藏 转发到动态 举报
写回复
用AI写文章
3 条回复
切换为时间正序
请发表友善的回复…
发表回复
李锐博恩 2020-05-11
  • 打赏
  • 举报
回复
引用 1 楼 宏强子的回复:
这样硬看,查不出问题还费时间,用modelsim仿真来查错吧
这是行家
joney_shi 2020-05-10
  • 打赏
  • 举报
回复
always@(posedge clk)
begin
case(current_state)
idle://等待
begin
改成
always@*
begin
case(current_state)
idle://等待
begin
芯王国 2020-05-10
  • 打赏
  • 举报
回复
这样硬看,查不出问题还费时间,用modelsim仿真来查错吧

5,313

社区成员

发帖
与我相关
我的任务
社区描述
硬件使用专区,欢迎大家讨论硬件相关内容 宝藏!数字IC精品文章收录(CSDN近500篇) http://t.csdn.cn/QbivO
社区管理员
  • 硬件使用社区
  • 张江打工人
加入社区
  • 近7日
  • 近30日
  • 至今

试试用AI创作助手写篇文章吧