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分享vhdl设计的秒表程序下载
vhdl设计的秒表程序
含有三个子模块
CNT10
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity CNT10 is
port(count:out std_logic_vector(3 downto 0);
cout:out std_logic;
cin,rst,clk:in std_logic);
end CNT10;
architecture behavioral of CNT10 is
signal counter:std_lo
相关下载链接：//download.csdn.net/download/xiaohuochai123/818111?utm_source=bbsseo
含有三个子模块
CNT10
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity CNT10 is
port(count:out std_logic_vector(3 downto 0);
cout:out std_logic;
cin,rst,clk:in std_logic);
end CNT10;
architecture behavioral of CNT10 is
signal counter:std_lo
相关下载链接：//download.csdn.net/download/xiaohuochai123/818111?utm_source=bbsseo
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