程序中包含了HAL_PWR_EnableBkUpAccess的实现，连接时报错，说没有。

[xrbaa]

如上图，编译连接时，总是报HAL_PWR_EnableBkUpAccess未定义，项目中包含了stm32f1xx_hal_pwr.c，stm32f1xx_hal_pwr.c中也定义了函数HAL_PWR_EnableBkUpAccess的实现。编译环境
keil5 ,示例程序是好的，不报错。请教大神们，这是什么原因啊？

[水滴重甲]

rtc.c里面包含了HAL_PWR_EnableBkUpAccess所在的.h文件么？
或者路径对不对？

[xrbaa]

引用 1 楼 水滴重甲 的回复:

rtc.c里面包含了HAL_PWR_EnableBkUpAccess所在的.h文件么？
或者路径对不对？

这个是rtc.c的代码

/* Includes ------------------------------------------------------------------*/
#include "rtc.h"

void HAL_PWR_EnableBkUpAccess(void);

/* USER CODE BEGIN 0 */

/* USER CODE END 0 */

RTC_HandleTypeDef hrtc;

/* RTC init function */
void MX_RTC_Init(void)
{

/**Initialize RTC Only
*/
hrtc.Instance = RTC;
hrtc.Init.AsynchPrediv = RTC_AUTO_1_SECOND;
hrtc.Init.OutPut = RTC_OUTPUTSOURCE_ALARM;
if (HAL_RTC_Init(&hrtc) != HAL_OK)
{
Error_Handler();
}

}

void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle)
{

if(rtcHandle->Instance==RTC)
{
/* USER CODE BEGIN RTC_MspInit 0 */

/* USER CODE END RTC_MspInit 0 */
// HAL_PWR_EnableBkUpAccess();




/* Enable BKP CLK enable for backup registers */
__HAL_RCC_BKP_CLK_ENABLE();
/* Peripheral clock enable */
__HAL_RCC_RTC_ENABLE();
/* USER CODE BEGIN RTC_MspInit 1 */

/* USER CODE END RTC_MspInit 1 */
}
}

void HAL_RTC_MspDeInit(RTC_HandleTypeDef* rtcHandle)
{

if(rtcHandle->Instance==RTC)
{
/* USER CODE BEGIN RTC_MspDeInit 0 */

/* USER CODE END RTC_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_RTC_DISABLE();
}
/* USER CODE BEGIN RTC_MspDeInit 1 */

/* USER CODE END RTC_MspDeInit 1 */
}

[xrbaa]

引用 1 楼 水滴重甲 的回复:

rtc.c里面包含了HAL_PWR_EnableBkUpAccess所在的.h文件么？
或者路径对不对？

这个是stm32f1xx_hal_pwr.c的代码：
空间限制，删除了好多注释。

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"


#ifdef HAL_PWR_MODULE_ENABLED

#define PVD_MODE_IT 0x00010000U
#define PVD_MODE_EVT 0x00020000U
#define PVD_RISING_EDGE 0x00000001U
#define PVD_FALLING_EDGE 0x00000002U
/* ------------- PWR registers bit address in the alias region ---------------*/
#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
#define PWR_CR_OFFSET 0x00U
#define PWR_CSR_OFFSET 0x04U
#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
/* --- CR Register ---*/
/* Alias word address of LPSDSR bit */
#define LPSDSR_BIT_NUMBER PWR_CR_LPDS_Pos
#define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPSDSR_BIT_NUMBER * 4U)))

/* Alias word address of DBP bit */
#define DBP_BIT_NUMBER PWR_CR_DBP_Pos
#define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U)))

/* Alias word address of PVDE bit */
#define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos
#define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U)))


/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static void PWR_OverloadWfe(void);

/* Private functions ---------------------------------------------------------*/
__NOINLINE
static void PWR_OverloadWfe(void)
{
__asm volatile( "wfe" );
__asm volatile( "nop" );
}


void HAL_PWR_DeInit(void)
{
__HAL_RCC_PWR_FORCE_RESET();
__HAL_RCC_PWR_RELEASE_RESET();
}

void HAL_PWR_EnableBkUpAccess(void)
{
/* Enable access to RTC and backup registers */
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
}

void HAL_PWR_DisableBkUpAccess(void)
{
/* Disable access to RTC and backup registers */
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
}
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
{
/* Check the parameters */
assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));

/* Set PLS[7:5] bits according to PVDLevel value */
MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);

/* Clear any previous config. Keep it clear if no event or IT mode is selected */
__HAL_PWR_PVD_EXTI_DISABLE_EVENT();
__HAL_PWR_PVD_EXTI_DISABLE_IT();
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();

/* Configure interrupt mode */
if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
{
__HAL_PWR_PVD_EXTI_ENABLE_IT();
}

/* Configure event mode */
if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
{
__HAL_PWR_PVD_EXTI_ENABLE_EVENT();
}

/* Configure the edge */
if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
{
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
}

if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
{
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
}
}

void HAL_PWR_EnablePVD(void)
{
/* Enable the power voltage detector */
*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
}

/**
* @brief Disables the Power Voltage Detector(PVD).
* @retval None
*/
void HAL_PWR_DisablePVD(void)
{
/* Disable the power voltage detector */
*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
}

void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
{
/* Check the parameter */
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
/* Enable the EWUPx pin */
*(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE;
}

void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
{
/* Check the parameter */
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
/* Disable the EWUPx pin */
*(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE;
}

void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
{
UNUSED(Regulator);

assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));

/* Clear SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));

/* Select SLEEP mode entry -------------------------------------------------*/
if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__SEV();
__WFE();
__WFE();
}
}

void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
{
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(Regulator));
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));

/* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */
CLEAR_BIT(PWR->CR, PWR_CR_PDDS);

/* Select the voltage regulator mode by setting LPDS bit in PWR register according to Regulator parameter value */
MODIFY_REG(PWR->CR, PWR_CR_LPDS, Regulator);

/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));

/* Select Stop mode entry --------------------------------------------------*/
if(STOPEntry == PWR_STOPENTRY_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__SEV();
PWR_OverloadWfe(); /* WFE redefine locally */
PWR_OverloadWfe(); /* WFE redefine locally */
}
/* Reset SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}

void HAL_PWR_EnterSTANDBYMode(void)
{
/* Select Standby mode */
SET_BIT(PWR->CR, PWR_CR_PDDS);

/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));

/* This option is used to ensure that store operations are completed */
#if defined ( __CC_ARM)
__force_stores();
#endif
/* Request Wait For Interrupt */
__WFI();
}


void HAL_PWR_EnableSleepOnExit(void)
{
/* Set SLEEPONEXIT bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}


void HAL_PWR_DisableSleepOnExit(void)
{
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}


/**
* @brief Enables CORTEX M3 SEVONPEND bit.
* @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
* WFE to wake up when an interrupt moves from inactive to pended.
* @retval None
*/
void HAL_PWR_EnableSEVOnPend(void)
{
/* Set SEVONPEND bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}


/**
* @brief Disables CORTEX M3 SEVONPEND bit.
* @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
* WFE to wake up when an interrupt moves from inactive to pended.
* @retval None
*/
void HAL_PWR_DisableSEVOnPend(void)
{
/* Clear SEVONPEND bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}



/**
* @brief This function handles the PWR PVD interrupt request.
* @note This API should be called under the PVD_IRQHandler().
* @retval None
*/
void HAL_PWR_PVD_IRQHandler(void)
{
/* Check PWR exti flag */
if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
{
/* PWR PVD interrupt user callback */
HAL_PWR_PVDCallback();

/* Clear PWR Exti pending bit */
__HAL_PWR_PVD_EXTI_CLEAR_FLAG();
}
}

/**
* @brief PWR PVD interrupt callback
* @retval None
*/
__weak void HAL_PWR_PVDCallback(void)

#endif /* HAL_PWR_MODULE_ENABLED */

[水滴重甲]

在rtc.c里面

void HAL_PWR_EnableBkUpAccess(void);

修改为：

extern void HAL_PWR_EnableBkUpAccess(void);

[xrbaa]

引用 4 楼 水滴重甲 的回复:

在rtc.c里面

void HAL_PWR_EnableBkUpAccess(void);

修改为：

extern void HAL_PWR_EnableBkUpAccess(void);

还是这个错误。

[水滴重甲]

我看你rtc.c里面的

/* USER CODE END RTC_MspInit 0 */
// HAL_PWR_EnableBkUpAccess();

这里不是注释掉了么，那你直接把最开始的
void HAL_PWR_EnableBkUpAccess(void); 也注释掉得了。

或者你在stm32f1xx_hal.h里面加个HAL_PWR_EnableBkUpAccess函数的申明，
然后再rtc.c里面 #include "stm32f1xx_hal.h"。

你都试试

[xrbaa]

引用 6 楼 水滴重甲 的回复:

我看你rtc.c里面的

/* USER CODE END RTC_MspInit 0 */
// HAL_PWR_EnableBkUpAccess();

这里不是注释掉了么，那你直接把最开始的
void HAL_PWR_EnableBkUpAccess(void); 也注释掉得了。

或者你在stm32f1xx_hal.h里面加个HAL_PWR_EnableBkUpAccess函数的申明，
然后再rtc.c里面 #include "stm32f1xx_hal.h"。

你都试试

非常感谢指导！
// HAL_PWR_EnableBkUpAccess();
这个注释掉后，能编译过去，但是运行错误。我粘贴时，粘贴了测试时的代码，抱歉！

刚才加了
#include "stm32f1xx_hal.h"
还是一样的错误。
太奇怪了。

[worldy]

运行错误，使用JLink调试，看看错在哪个位置

[xrbaa]

引用 8 楼 worldy 的回复:

运行错误，使用JLink调试，看看错在哪个位置

生成hex、axf文件前报的错。没有axf文件可以调试吗？
好像是连接错误。

[帮帮你我她]

库文件添加入工程后，还需在配置文件xxxconf.h打开相应外设，取消屏蔽就好了

[xrbaa]

引用 10 楼 帮帮你我她 的回复:

库文件添加入工程后，还需在配置文件xxxconf.h打开相应外设，取消屏蔽就好了

这些都做了。