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分享十进制计数器VHDL下载
通过VHDL，实现10位带使能计数器。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT10 IS
PORT(CLK_IN: IN STD_LOGIC;
COUT228 : OUT STD_LOGIC); --计数进位输出
END CNT10;
ARCHITECTURE behav OF CNT10 IS
SIGNAL Q : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
REG: PROCESS
相关下载链接：//download.csdn.net/download/mikezxy/5488035?utm_source=bbsseo
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT10 IS
PORT(CLK_IN: IN STD_LOGIC;
COUT228 : OUT STD_LOGIC); --计数进位输出
END CNT10;
ARCHITECTURE behav OF CNT10 IS
SIGNAL Q : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
REG: PROCESS
相关下载链接：//download.csdn.net/download/mikezxy/5488035?utm_source=bbsseo
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