请班竹帮忙呀!小弟搞了一个星期了。
小弟现在想写一个测试浮点运算是否正确的程序:而且小弟也有相应的汇编代码,但是现在我想在VC下来实现,但我不是很清楚,他的原理,我尝试着把汇编代码转换为VC代码,但是总是没有成功,请班竹帮忙呀。下面是我要转换的汇编代码。
CARRY_ERROR EQU 1
REG_BITS_ERROR EQU 2
FLAGS_ERROR EQU 3
BCD_ERROR EQU 4
MUL_DIV_ERROR EQU 5
JMP_ERROR EQU 6
MUL386_ERROR EQU 7
LOGIC1_ERROR EQU 8
LOGIC2_ERROR EQU 9
CMPS_ERROR EQU 10
IOS_ERROR EQU 11
STRS_ERROR EQU 12
MOVS_ERROR EQU 13
PUSHA_ERROR EQU 14
NUM_REG = 8 ; NUMBER OF REGISTERS IN THE NPX
NUM_BITS = 64 ; # of bits to test in the significant
NUM_EXP = 14 ; # of bits to test in the exponent
;*****************************************************************************
;_ChkFpuArith
; Test FPU Arithmetics
; Entry: None
; Exit: AX=1 if PASS , AX=0 if Fail
;*****************************************************************************
PUBLIC _ChkFpuArith
_ChkFpuArith PROC far
push ds
push es
push bx
push si
push di
mov ax,CPUGROUP
mov ds,ax
finit ; initialize the npx
cli ; disable intrerrupts. then load the
mov control_word,133fh ; ctrl word: no exceptions, no interrupts
fldcw control_word ; 64 bits, round even, infinity affine
mov reg_counter,num_reg ; for each register do:
t001:
fild ds:two ; initialize register
mov bit_counter,num_bits ; for each bit in the significand field:
t002:
call check_significand ; if carry bit not set, flag error
jc short t004 ; and return
fimul ds:two ; generate carry (register*2)
fisub ds:one ; move bit to the right (register-1)
dec bit_counter
jnz short t002 ; end for
fstp st(0) ; initialize register (store and pop)
fild ds:four ; integer load 4
mov bit_counter,num_exp ; for each bit in the exponent field do:
t003:
call check_exponent ; if exponent incorrect, return
jc short t004 ;
fmul st,st(0) ; squares the content of the stack top
fidiv ds:two ; divide by two, sets next bit in exponent
dec bit_counter
jnz short t003 ; end for
xor ax,ax ; zero expected condition bits.
call condition_bits ; if register <> positive & nonzero
t004:
jnz short t007 ; flag error and return
fchs ; generate a nan (sqrt(-number))
fsqrt
mov ah,045h ; set expected condition bits.
call condition_bits ; if register <> (nan or infinity)
jnz short t007 ; flag error and return
fstp st(0) ; store and pop. initialize register 0
fldz ; load +0.0 into stack 0
mov ah,040h ; set expected condition bits.
call condition_bits ; if register <> zero (+ or -)
jnz short t007 ; flag error and return
fsub ds:alarge ; make register negitive and nonzero
mov ah,001h ; set expected condition bits.
call condition_bits ; if register <> negitive and nonzero
jnz short t007 ; flag error and return
dec reg_counter ; endif
jz short t006 ;
jmp t001
t006:
call check_stack ; check each register for -large
jz short t008
t007:
mov ax,0
jmp @F
t008:
mov ax,1
@@:
sti
pop di
pop si
pop bx
pop es
pop ds
retf
_ChkFpuArith ENDP