Quartus18.0 FIR IP核使用问题

[csdnjainyu]

按照教程一步一步设置好，然后MODELSIM仿真时遇见如下警告，仿真不出来，有大神教下小弟吗，感激不尽

 

[csdnjainyu]

IP核只设置了位宽，采样速率，符号速率，其他的包括滤波器系数都是默认，另外IP核报了几个警告，不知道相不相关
Warning (10036): Verilog HDL or VHDL warning at fir_ip_0002.vhd(54): object "coeff_in_read_sig" assigned a value but never read
Warning (10541): VHDL Signal Declaration warning at fir_ip_0002_ast.vhd(208): used implicit default value for signal "core_channel_out_core" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.

[csdnjainyu]

@周三岁 我就是按照这个链接教程一步步来的

[csdnjainyu]

@周三岁 https://blog.csdn.net/qq_42839007/article/details/104354810?ops_request_misc=&;request_id=&biz_id=102&utm_term=quartusFIR%20IP%E6%A0%B8&utm_medium=distribute.pc_search_result.none-task-blog-2~blog~sobaiduweb~default-2-104354810.nonecase&spm=1018.2226.3001.4450

[周三岁]

兄弟，你的18.0 FIR IP核使用教程可以分享一下吗！