verilog基础问题求助

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Verilog 基础知识(一) Verilog 基础语法与注意事项本文主要介绍了硬件描述语言：Verilog HDL的一些常用语法及注意事项。阅读详情

编写16位*16位booth加法器，模拟时reset信号一置1（低位有效），输出就变红xxxx，折腾好久弄不明白原因在哪，求助大佬

图为模拟

代码如下

module booth_multiply(
    input  clk,
    input  reset,
    input [15:0]  a,
    input [15:0]  b,
    output reg [31:0]   z
);

reg [32:0] multiplicand, accumulator;
reg [16:0] multiplier;
integer i;

always @(posedge clk) begin
    if (!reset) begin
        z <= 32'h0;
    end 
    else begin
        multiplier[16:0] <= {1'b0, b};
        multiplicand[32:0] <= {17'h0, a};
        accumulator[32:0] <= 33'h0;
        
        for (i = 0; i < 16; i = i+1) begin
            case (multiplier[1:0])
                2'b00, 2'b11: begin
                    // Do nothing
                end
                2'b01: begin
                    accumulator <= accumulator + multiplicand;
                end
                2'b10: begin
                    accumulator <= accumulator - multiplicand;
                end
            endcase
            
            accumulator[32:0] <= {accumulator[31:0], multiplier[0]};
            multiplier[16:0] <= {multiplier[15:1], accumulator[32]};
            multiplicand[32:0] <= {multiplicand[31], multiplicand[32:1]};          
        end        
       z <= accumulator[31:0];
    end
end

endmodule

`timescale  1ns / 1ps    

module tb_booth_multiply;

parameter DATAWIDTH  = 16;

reg   clk                                  = 0 ;
reg   reset                                = 0 ;
reg   [ DATAWIDTH - 1 : 0 ]  a             = 0 ;
reg   [ DATAWIDTH - 1 : 0 ]  b             = 0 ;
wire    [ DATAWIDTH * 2 - 1 : 0 ]  z        = 0 ;
   
always #5 clk=~clk;
initial
begin
    reset =0;
    clk=1;
end


booth_multiply e(
.clk(clk),.reset(reset),.a(a),.b(b),.z(z)
);

initial
begin
#20
    reset = 0;
#20
    reset = 1;
    a = 16;
    b = 4;
#100
reset = 0;
end
endmodule

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