基于Cyclone 10LP FPGA设计OV5640摄像头采集HDMI显示例程Verilog逻辑例程源码quartusg工程文件
module ov5640_sdram_hdmi(
input clk,
input rst_n,
//sdram control
output sdram_clk,
output sdram_cke,
output sdram_cs_n,
output sdram_we_n,
output sdram_cas_n,
output sdram_ras_n,
output [1:0] sdram_dqm,
output [1:0] sdram_ba,
output [12:0] sdram_addr,
inout [15:0] sdram_dq,
//cmos interface
output camera_sclk,
inout camera_sdat,
input camera_vsync,
input camera_href,
input
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