Vrilog Language练习(1 basics)|“朝闻道”知识分享大赛“

[i oy]

这是我参加“朝闻道”知识分享大赛的第4篇文章。

 

1 AND GATE

 

module top_module( 
    input a, 
    input b, 
    output out );
assign out = a & b;
endmodule

2 NOR GATE

module top_module( 
    input a, 
    input b, 
    output out );
    assign out = !(a | b);
endmodule

3 XNOR GATE

 

module top_module( 
    input a, 
    input b, 
    output out );
    assign out = !(a ^ b);    

endmodule

4 7458 chip

 

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
    assign p1y = ((p1a & p1b & p1c)|(p1d & p1e & p1f));
    assign p2y = ((p2a & p2b)|(p2c & p2d)); 

endmodule