关于Stream Bufer Engine和TV Technologies的一个问题.

dreameasy 2005-07-11 11:52:32
(本人开贴,无论大小问题,一概100分起价)

背景资料:

Stream Buffer Engine用于Seek,Pause,Record一个实时的视频流,用于实现PVR和Time Shift功能.
关键之处,在于把视频流录成文件.

为了测试SBE的录这一功能,我试验了下面的连接

--->mpeg2 video--------
file source(某mpeg2电影文件) --- mpeg2 demux--| |--->SBE Sync Filter
-->mpeg2 audio--------

将一个mpeg2视频文件demux成video和audio,然后连接到SBE Sync filter上,用IStreamBufferSink接口的CreateRecorder方法创建一个录制对象.然后,调用 IStreamBufferRecordControl接口的Start方法,开始录制.

下面是部分关键代码:

const IID IID_IStreamBufferSink = {
0xafd1f242 , 0x7efd , 0x45ee , 0xba , 0x4e, 0x40, 0x7a, 0x25, 0xc9, 0xa7, 0x7a};
/* Get the IStreamBufferSink interface */
hr = m_pStreamBufferSyncFilter->QueryInterface(
IID_IStreamBufferSink,
(void **)&m_pStreamBufferSyncInterface);

hr = m_pStreamBufferSyncInterface->LockProfile(L"g:\\test.sbe");

_unlink ("g:\\test.dvr-ms");
hr = m_pStreamBufferSyncInterface->CreateRecorder(L"g:\\test.dvr-ms", 0,&m_pRecUnk);

hr = m_pMC->Run();


...
CComQIPtr<IStreamBufferRecordControl> pRecControl(m_pRecUnk);
REFERENCE_TIME rtStart = 0;
hr = pRecControl->Start(&rtStart);


上面的程序在winxp sp2 下测试通过.得到了一个dvr-ms (microsoft tv show)文件.

请各位读者认真体会我上面的内容,然后看我下面的问题:
(1)我最终的目的,其实是要操控PC上的电视卡,录制电视节目(PVR),实现时间跳转(Time Shift)功能,上面仅仅是对SBE的测试.
在这里,我并没有列出用Stream Buffer Source和上述Stream Buffer Sync进行关联,从而实现Time Shift功能的代码.

(2)如果我有一块数字电视卡(Digital TV),即,电视卡会提供一个类似于mpeg2 file source filter等价的一个源.那么,我上面的测试程序几乎可以照搬。
但是,如果我只有一块模拟电视卡(Analog TV),那么,我需要自己进行mpeg2 encode,filter graph如下:
Analog TV --> mpeg2 video encode--
|-->SBE sync filter
Audio capture --> mpeg audio encode --

按照设想,我觉得对于SBE sync而言,这和上面的例子并无太大区别.

可是,结果是,我发现,这个时候SBE sync并没有得到我期望中的产出物:dvr-ms文件.

问题出在什么地方呢?
我能区定几点:
(1)程序并无问题.
(2)mpeg2 encode无问题.


请各位大侠提供一点思路~~~

我觉得这个问题有点点复杂,请大家帮帮忙~~~
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renhappy 2006-02-24
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ds不好用,还是自己的engine好用,至少知道错在哪里

btw,有错误码吗?
dreameasy 2006-02-23
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up!
dreameasy 2006-02-23
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up!
Table of Contents 1 Myriad 2 Platorm...................................................................................................................6 1.1 Overview......................................................................................................................................6 1.2 Hardware Summary.....................................................................................................................7 1.3 IC nomenclature...........................................................................................................................8 2 Top-Level System....................................................................................................................9 2.1 MA245x Bus Interconnect...........................................................................................................9 2.2 Boot Operanon..........................................................................................................................16 2.3 Secure Boot................................................................................................................................46 3 CPU Sub-system....................................................................................................................52 3.1 LEON4 – High-performance SPARC V8 32-bit Processor............................................................52 3.2 GRFPU – High-performance IEEE-754 Floanng-point unit.........................................................74 3.3 DSU4 – LEON4 Hardware Debug Support Unit..........................................................................81 3.4 Leon L2C – Level 2 Cache controller for the Leons....................................................................98 3.5 Interrupt Controller.................................................................................................................114 3.6 Timers......................................................................................................................................123 3.7 Clock, Power and Reset Control...............................................................................................131 3.8 AON block................................................................................................................................159 3.9 Retennon Register...................................................................................................................163 3.10 Temperature Sensors.............................................................................................................166 3.11 USB Controller........................................................................................................................170 3.12 USB PHY.................................................................................................................................424 3.13 Mobile Storage/SDIO.............................................................................................................476 3.14 Gigabit Ethernet Media Access Controller (MAC).................................................................644 3.15 AHB_DMA..............................................................................................................................659 3.16 APB_I2S..................................................................................................................................809 3.17 APB_I2C..................................................................................................................................847 3.18 APB_SPI..................................................................................................................................936 3.19 APB_UART............................................................................................................................1011 3.20 GPIO Interface......................................................................................................................1075 3.21 JTAG Interface......................................................................................................................1097 4 SHAVE Protessor Core.......................................................................................................1099 4.1 Local Address Space Control Unit..........................................................................................1099 4.2 L1 Caches...............................................................................................................................1100 4.3 Translanon Lookaside Bufer..................................................................................................1103 4.4 Interrupt Request Support.....................................................................................................1105 4.5 Register Files..........................................................................................................................1105 4.6 SHAVE Instrucnon Set Architecture.......................................................................................1124 4.7 Register Interface...................................................................................................................1320 4.8 SHAVE Debug & Control Unit (DCU)......................................................................................1326 5 Protessor Memory Blotk (PMB)........................................................................................1347 5.1 CMX Memory System............................................................................................................1347 5.2 CMX FIFO...............................................................................................................................1358 Intel® Movidius™ Confdennal 3 MA245x-DB-1.02 Released to Shanghai Spetek Information Technology Development Co., Ltd. Per Intel CNDA# cnda023213 5.3 CMX DMA Controller.............................................................................................................1364 5.4 Bicubic Filter..........................................................................................................................1387 5.5 Myriad 2 Mutex Controller....................................................................................................1411 5.6 SHAVE L2 Cache.....................................................................................................................1417 6 DRAM Subsystem..............................................................................................................1430 6.1 DDR Controller.......................................................................................................................1430 6.2 DDR PHY.................................................................................................................................1485 7 Media Subsystem (MSS)....................................................................................................1672 7.1 Overview................................................................................................................................1672 7.2 Feature Set.............................................................................................................................1672 7.3 Block diagrams.......................................................................................................................1673 7.4 Architecture...........................................................................................................................1673 7.5 Sofware Driver Notes............................................................................................................1681 7.6 Register Interface...................................................................................................................1688 7.7 Camera Interface...................................................................................................................1703 7.8 LCD Controller / Video Out....................................................................................................1738 7.9 NAL.........................................................................................................................................1793 7.10 MIPI Controller.....................................................................................................................1822 7.11 MIPI D-PHY Bidir 2L..............................................................................................................1889 7.12 Streaming Image Processing Pipeline Accelerators.............................................................1994 7.13 Accelerator Memory Controller...........................................................................................2187 8 Power Management..........................................................................................................2195 8.1 Power Management Features...............................................................................................2195 8.2 Power Island defninons........................................................................................................2197 8.3 Power states...........................................................................................................................2199 8.4 Core voltages.........................................................................................................................2204 8.5 Dynamic Frequency scaling support......................................................................................2204 9 Elettrital...........................................................................................................................2206 9.1 Overview................................................................................................................................2206 9.2 Chip Operanng Condinons.....................................................................................................2206 9.3 GPIO Pins................................................................................................................................2208 9.4 Operanng ranges....................................................................................................................2219 10 Patkage...........................................................................................................................2220 10.1 Overview..............................................................................................................................2220 10.2 Package Thermal Informanon..............................................................................................2222 10.3 Solder Refow Profle...........................................................................................................2222 10.4 Moisture Sensinvity Level (MSL)..........................................................................................2223 10.5 Restricnon On Hazardous Substances (ROHS) compliance.................................................2223 10.6 VFBGA Package Ball out.......................................................................................................2224 10.7 BGA Package Outline...........................................................................................................2225 11 Movidius Produtt Ordering Informaton..........................................................................2226 11.1 Product Ordering Codes......................................................................................................2226 11.2 Product Ordering Opnons....................................................................................................2226 11.3 Minimum Order Requirements...........................................................................................2227 Intel® Movidius™ Confdennal 4 MA245x-DB-1.02 Released to Shanghai Spetek Information Technology Development Co., Ltd. Per Intel CNDA# cnda023213 11.4 MA245x Delivery Tray..........................................................................................................2228

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