求用VHDL设计FIFO的例子

baggiofans 2006-04-12 05:03:59
我是一菜鸟,欲学习用FPGA实现FIFO,想用VHDL语言设计.由于没有经验,无从下手,诸位高手可否不吝赐教.有实例,代码,资料什么的就更好了.虚心请教.望大虾们帮助.谢谢先!
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baggiofans 2006-05-09
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也就是说,只要FPGA中内嵌了异步双口RAM,就可以实现我所说的功能——同时读写的FIFO,是吗~
woodwoodwood3 2006-04-28
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这东西三言两语是讲不清的,可以到 http://www.free-ip.com去瞧瞧。

Introduction
The ram_dp2 component is a full dual port RAM. Unlike the original ram_dp component, ram_dp2 has two ports which are capable of both reads and writes (ram_dp has one write-only port and another read-only port). Of course, this ability comes at a price-- portability and flexability. The ram_dp2 component is not as portable as the basic ram_dp, and it does not offer as many options.

Component Declaration
The basic component declaration of the Free-RAM dual port module is:

component ram_dp2
generic (addr_bits :integer;
data_bits :integer;
block_type :integer := 0);
port (reset :in std_logic;
p1_clk :in std_logic;
p1_we :in std_logic;
p1_addr :in std_logic_vector (addr_bits-1 downto 0);
p1_din :in std_logic_vector (data_bits-1 downto 0);
p1_dout :out std_logic_vector (data_bits-1 downto 0);

p2_clk :in std_logic;
p2_we :in std_logic;
p2_addr :in std_logic_vector (addr_bits-1 downto 0);
p2_din :in std_logic_vector (data_bits-1 downto 0);
p2_dout :out std_logic_vector (data_bits-1 downto 0)
);
end component;


Generic Map
The generic portion of the component has parameters for the number of address and data bits, plus flags to specify read modes and optimization hints. The parameters are:

addr_bits -- The number of bits on the address bus (same for reads and writes).

data_bits -- The number of bits on the data bus (same for reads and writes).

block_type -- Signals to the RAM core what type of RAM should be used.
0 = Automatic, the RAM core decides what is most appropriate.


Note that the ram_dp2 component doesn't have a register_out_flag. The ram_dp2 operates only with synchronous reads.

Also note that while the block_type is defined, it is not currently used. The Free-RAM core will always use the most appropriate RAM type.

Port Map
Aside from the common reset signal, the ram_dp2's two ports are identical so we'll only describe one:

reset -- An asynchronous reset signal.

clk -- The clock used for reads and writes of the port.

we -- The write enable signal (1=enabled).

addr -- The port address bus.

din -- Input data for the port.

dout -- Output data for the port.



Read and Write Timing
The read and write timing is identical to the ram_dp component (assuming that register_out_flag=1).
baggiofans 2006-04-28
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大侠,我是菜鸟,您能讲详细些吗。一般的FPGA中本身就是有RAM的,您说的异步双口RAM到底是什么概念呢?谢谢谢谢。
baggiofans 2006-04-26
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您能再详细说一下吗,是FPGA中就带有双口异步RAM吗,它有两根地址线可以实现同时读写功能是吗?谢谢。
woodwoodwood3 2006-04-26
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直接将RAM做在FPGA里面
woodwoodwood3 2006-04-24
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当然可以,我的同事做过,双口异步RAM。
baggiofans 2006-04-24
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大侠,我还有一个问题,我们想用RAM实现一个异步的FIFO,就是同时可以读写的.在FPGA中可以做到吗?如果可以,怎么实现两条地址线呢,因为RAM的地址线是一根啊.谢谢
woodwoodwood3 2006-04-14
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quartus2
baggiofans 2006-04-14
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谢谢您,您做开发使用的是什么环境,我们使用的是ISE,初学起来应该注意些什么呢?
woodwoodwood3 2006-04-12
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给点代码参考吧:


library IEEE;
use IEEE.Std_logic_1164.all;

entity FIFOMXN is
generic(m, n : Positive := 8); --m is fifo depth, n is fifo width
port(RESET, WRREQ, RDREQ, CLOCK : in Std_logic;
DATAIN : in Std_logic_vector((n-1) downto 0);
DATAOUT : out Std_logic_vector((n-1) downto 0);
FULL, EMPTY : inout Std_logic);
end FIFOMXN;

architecture V2 of FIFOMXN is

type Fifo_array is array(0 to (m-1)) of Bit_vector((n-1) downto 0);
signal Fifo_memory : Fifo_array;
signal Wraddr, Rdaddr, Offset : Natural range 0 to (m-1);
signal Rdpulse, Wrpulse, Q1, Q2, Q3, Q4 : Std_logic;
signal Databuffer : Bit_vector((n-1) downto 0);

begin

--pulse synchronisers for WRREQ and RDREQ
--modified for Synplify to a process

sync_ffs : process
begin
wait until rising_edge(CLOCK);
Q1 <= WRREQ;
Q2 <= Q1;
Q3 <= RDREQ;
Q4 <= Q3;
end process;

--concurrent logic to generate pulses

Wrpulse <= Q2 and not(Q1);
Rdpulse <= Q4 and not(Q3);


Fifo_read : process
begin
wait until rising_edge(CLOCK);
if RESET = '1' then
Rdaddr <= 0;
Databuffer <= (others => '0');
elsif (Rdpulse = '1' and EMPTY = '0') then
Databuffer <= Fifo_memory(Rdaddr);
Rdaddr <= (Rdaddr + 1) mod m;
end if;
end process;


Fifo_write : process
begin
wait until rising_edge(CLOCK);
if RESET = '1' then
Wraddr <= 0;
elsif (Wrpulse = '1' and FULL = '0') then
Fifo_memory(Wraddr) <= To_Bitvector(DATAIN);
Wraddr <= (Wraddr + 1) mod m;
end if;
end process;

Offset <= (Wraddr - Rdaddr) when (Wraddr > Rdaddr)
else (m - (Rdaddr - Wraddr)) when (Rdaddr > Wraddr)
else 0;

EMPTY <= '1' when (Offset = 0) else '0';
FULL <= '1' when (Offset = (m-1)) else '0';

DATAOUT <= To_Stdlogicvector(Databuffer) when RDREQ = '0'
else (others => 'Z');

end V2;

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