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IntelPerLib 2006-12-22
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还是大家仔细:
Instructions
MMX,SSE,SSE2,SSE3,SSE4,EM64T
还是改为:
Instructions
MMX,SSE,SSE2,SSE3,SSSE3,EM64T
为妥.
Instructions
MMX,SSE,SSE2,SSE3,SSE4,EM64T
还是改为:
Instructions
MMX,SSE,SSE2,SSE3,SSSE3,EM64T
为妥.
flyingdog 2006-12-21
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其实对于本次优化，由于是使用double类型的。所以主要起作用的应该是SSE2里面对double的操作。其实SSE指令集都没有需要的指令。
flyingdog 2006-12-21
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根据intel的文档。
The Intel Xeon processor 5100 series, Intel
Core 2 processor families introduced Supplemental Streaming SIMD Extensions 3
(SSSE3).
应该Core2是提供了SSSE3的，SSSE3估计就是你说的SSE4。
SSSE3 provides 32 instructions to accelerate a variety of multimedia and signal
processing applications employing SIMD integer data.
一共包含如下指令：
• Twelve instructions that perform horizontal addition or subtraction operations.
• Six instructions that evaluate the absolute values.
• Two instructions that perform multiply and add operations and speed up the
evaluation of dot products.
• Two instructions that accelerate packed-integer multiply operations and produce
integer values with scaling.
• Two instructions that perform a byte-wise, in-place shuffle according to the
second shuffle control operand.
• Six instructions that negate packed integers in the destination operand if the
signs of the corresponding element in the source operand is less than zero.
• Two instructions that align data from the composite of two operands.
The Intel Xeon processor 5100 series, Intel
Core 2 processor families introduced Supplemental Streaming SIMD Extensions 3
(SSSE3).
应该Core2是提供了SSSE3的，SSSE3估计就是你说的SSE4。
SSSE3 provides 32 instructions to accelerate a variety of multimedia and signal
processing applications employing SIMD integer data.
一共包含如下指令：
• Twelve instructions that perform horizontal addition or subtraction operations.
• Six instructions that evaluate the absolute values.
• Two instructions that perform multiply and add operations and speed up the
evaluation of dot products.
• Two instructions that accelerate packed-integer multiply operations and produce
integer values with scaling.
• Two instructions that perform a byte-wise, in-place shuffle according to the
second shuffle control operand.
• Six instructions that negate packed integers in the destination operand if the
signs of the corresponding element in the source operand is less than zero.
• Two instructions that align data from the composite of two operands.
housisong 2006-12-21
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Core2加入了32条额外的附加流指令集做为SSE3的补充
后来的45nm Core2 Extreme 有SSE4？
后来的45nm Core2 Extreme 有SSE4？
housisong 2006-12-21
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（道听途说）好像说Core2的SSE4实现还不完整，刚开始媒体宣传的时候有，发布以后更正说没有
flyingdog 2006-12-21
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SSE4?
根据Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 1:Basic Architecture的文档说明，应该是Supplemental Streaming SIMD Extensions 3(SSSE3)吧。
根据Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 1:Basic Architecture的文档说明，应该是Supplemental Streaming SIMD Extensions 3(SSSE3)吧。
celineshi 2006-12-21
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详细的测试环境的配置如下，请参考
CPU
Processor
Intel(R) Core(TM) 2 Duo E6400 @ 2.13GHz (Allendale)
Instructions
MMX,SSE,SSE2,SSE3,SSE4,EM64T
Core Speed
2131.1MHz
Bus Speed
266.4MHz
Rated FSB
1065.6MHz
L1 Data Cache
32KB*2
L1 Instruction Cache
32KB*2
L2 Cache
2MB*1 (Share)
Enable EM64T
Yes
Enable HT Tech
No
Mainboard
Intel DQ965GF Chipset
Memory
DDR2 1GB
OS
MS Windows XP Professional SP2 (32bit)
DirectX 9.0c
CPU
Processor
Intel(R) Core(TM) 2 Duo E6400 @ 2.13GHz (Allendale)
Instructions
MMX,SSE,SSE2,SSE3,SSE4,EM64T
Core Speed
2131.1MHz
Bus Speed
266.4MHz
Rated FSB
1065.6MHz
L1 Data Cache
32KB*2
L1 Instruction Cache
32KB*2
L2 Cache
2MB*1 (Share)
Enable EM64T
Yes
Enable HT Tech
No
Mainboard
Intel DQ965GF Chipset
Memory
DDR2 1GB
OS
MS Windows XP Professional SP2 (32bit)
DirectX 9.0c
