谁能解释下mrc p15,0,r0,c1,c0,0？把我搞死了

crtd024 2008-01-09 02:27:49

谁能解释下mrc p15,0,r0,c1,c0,0？把我搞死了

...全文

4500 8 打赏收藏转发到动态举报

写回复

8 条回复

切换为时间正序

请发表友善的回复…

发表回复

gooogleman 2008-10-13

打赏
举报

回复

3.9.1 Enabling the MMU

To enable the MMU:

1. Program the TTB and domain access control registers.

2. Program level 1 and level 2 page tables as required.

3. Enable the MMU by setting bit 0 in the control register.

You must take care if the translated address differs from the untranslated address 

because several instructions following the enabling of the MMU might have been 

prefetched with the MMU off (using physical = VA - flat translation).

In this case, enabling the MMU can be considered as a branch with delayed execution. 

A similar situation occurs when the MMU is disabled. Consider the following code 

sequence:

MRC p15,0,R1,C1,C0,0 ; Read control register

ORR R1, #0x1

MCR p15,0,R1,C1,C0,0  ; Enable MMUS

Fetch Flat

Fetch Flat

Fetch Translated

You can enable the ICache and DCache simultaneously with the MMU using a single 

MCR instruction.

UltraBejing 2008-05-01

打赏
举报

回复

我也想了解，谢谢LZ.

meiZiNick 2008-05-01

打赏
举报

回复

支持搂主，收藏

chenpuyi 2008-03-11

打赏
举报

回复

读取控制寄存器,这包括 MMU,cache,writebuffer 的打开与关闭.
读出修改后再用 mcr p15,0,r0,c1,c0,0 写回去.

ppzzhhsky 2008-03-06

打赏
举报

回复

谁能解释下mrc p15,0,r0,c1,c0,0？把我搞死了
将协处理器p15的寄存器中的数据传送到ARM处理器的寄存器r0中,其中1是协处理器操作码1,0是协处理器操作码2,c1存放第一个操作数的协处理器寄存器,c0存放第二个操作数的协处理器寄存器

yujianhuabcde 2008-02-29

打赏
举报

回复 3

[转帖]<MCR|MRC>{cond} p#,<expression1>,Rd,cn,cm{,<expression2>}
MRC 从协处理器移到ARM7寄存器（L=1）
MCR 从ARM7寄存器移到协处理器（L=0）
{cond} 两个字符的条件代码
p# 被请求得协处理器的惟一标识苻
<expression1> 计算一个常量并放到CP Opc域
Rd 是一个表达式计算ARM7有效寄存器序号
cn 和cm 是计算有效协处理器寄存器CRn CRm序号
<expression2> 计算一个常量，并放到CP域
4.13.6 举例
MRC 2,5,R3,c5,c6 ;请求协处理器2 执行操作5 ，操作数为c5和c6，
; 传送结果到R3 (单次32位字)
MCR 6,0,R4,c6 ; 请求协处理器6执行操作0，操作数为R4
;结果送到c6
来自ARM7 数据手册

唐勉的技术博客 2008-01-10

打赏
举报

回复

mrc是协处理器命令。用于读取协处理器中的寄存器的数据到ARM处理器的寄存器里面。这句话的意思应该是读协处理器中的寄存器数据到ARM处理器的r0里面。应该是ARM访问MMU，一般cp15就是MMU。

crtd024 2008-01-09

打赏
举报

回复

arm9的一个协处理器指令。。。。

ARM实验仅供参考;//===================================================================== ;// File Name : 2410slib.s ;// Function : S3C2410 (Assembly) ;// Program : Shin, On Pil (SOP) ;// Date : March 20, 2002 ;// Version : 0.0 ;// History ;// 0.0 : Programming start (February 26,2002) -> SOP ;//===================================================================== ;//Interrupt, FIQ/IRQ disable NOINT EQU 0xc0 ;//1100 0000 ;//Check if tasm.exe(armasm -16 ...@ADS 1.0) is used. GBLL THUMBCODE [ {CONFIG} = 16 THUMBCODE SETL {TRUE} CODE32 | THUMBCODE SETL {FALSE} ] MACRO MOV_PC_LR [ THUMBCODE bx lr | mov pc,lr ] MEND AREA |C$$code|, CODE, READONLY ;//============== ;// CPSR I,F bit ;//============== ;//int SET_IF(void); ;//The return value is current CPSR. EXPORT SET_IF SET_IF ;//This function works only if the processor is in previliged mode. mrs r0,cpsr mov r1,r0 orr r1,r1,#NOINT msr cpsr_cxsf,r1 MOV_PC_LR ;//void WR_IF(int cpsrValue); EXPORT WR_IF WR_IF ;//This function works only if the processor is in previliged mode. msr cpsr_cxsf,r0 MOV_PC_LR ;//void CLR_IF(void); EXPORT CLR_IF CLR_IF ;//This function works only if the processor is in previliged mode. mrs r0,cpsr bic r0,r0,#NOINT msr cpsr_cxsf,r0 MOV_PC_LR ;//==================================== ;// MMU Cache/TLB/etc on/off functions ;//==================================== R1_I EQU (1<<12) R1_C EQU (1<<2) R1_A EQU (1<<1) R1_M EQU (1) R1_iA EQU (1<<31) R1_nF EQU (1<<30) ;//void MMU_EnableICache(void) EXPORT MMU_EnableICache MMU_EnableICache mrc p15,0,r0,c1,c0,0 orr r0,r0,#R1_I mcr p15,0,r0,c1,c0,0 MOV_PC_LR ;//void MMU_DisableICache(void) EXPORT MMU_DisableICache MMU_DisableICache mrc p15,0,r0,c1,c0,0 bic r0,r0,#R1_I mcr p15,0,r0,c1,c0,0 MOV_PC_LR ;//void MMU_EnableDCache(void) EXPORT MMU_EnableDCache MMU_EnableDCache mrc p15,0,r0,c1,c0,0 orr r0,r0,#R1_C mcr p15,0,r0,c1,c0,0 MOV_PC_LR ;//void MMU_DisableDCache(void) EXPORT MMU_DisableDCache MMU_DisableDCache mrc p15,0,r0,c1,c0,0 bic r0,r0,#R1_C mcr p15,0,r0,c1,c0,0 MOV_PC_LR ;//void MMU_EnableAlignFault(void) EXPORT MMU_EnableAlignFault MMU_EnableAlignFault mrc p15,0,r0,c1,c0,0 orr r0,r0,#R1_A mcr p15,0,r0,c1,c0,0 MOV_PC_LR ;//void MMU_DisableAlignFault(void) EXPORT MMU_DisableAlignFault MMU_DisableAlignFault mrc p15,0,r0,c1,c0,0 bic r0,r0,#R1_A mcr p15,0,r0,c1,c0,0 MOV_PC_LR ;//void MMU_EnableMMU(void) EXPORT MMU_EnableMMU MMU_EnableMMU mrc p15,0,r0,c1,c0,0 orr r0,r0,#R1_M mcr p15,0,r0,c1,c0,0 MOV_PC_LR ;//void MMU_DisableMMU(void) EXPORT MMU_DisableMMU MMU_DisableMMU mrc p15,0,r0,c1,c0,0 bic r0,r0,#R1_M mcr p15,0,r0,c1,c0,0 MOV_PC_LR ;//void MMU_SetFastBusMode(void) ;// FCLK:HCLK= 1:1 EXPORT MMU_SetFastBusMode MMU_SetFastBusMode mrc p15,0,r0,c1,c0,0 bic r0,r0,#R1_iA:OR:R1_nF mcr p15,0,r0,c1,c0,0 MOV_PC_LR ;//void MMU_SetAsyncBusMode(void) ;// FCLK:HCLK= 1:2 EXPORT MMU_SetAsyncBusMode MMU_SetAsyncBusMode mrc p15,0,r0,c1,c0,0 orr r0,r0,#R1_nF:OR:R1_iA mcr p15,0,r0,c1,c0,0 MOV_PC_LR ;//========================= ;// Set TTBase ;//========================= ;//void MMU_SetTTBase(int base) EXPORT MMU_SetTTBase MMU_SetTTBase ;//ro=TTBase mcr p15,0,r0,c2,c0,0 MOV_PC_LR ;//========================= ;// Set Domain ;//========================= ;//void MMU_SetDomain(int domain) EXPORT MMU_SetDomain MMU_SetDomain ;//ro=domain mcr p15,0,r0,c3,c0,0 MOV_PC_LR ;//========================= ;// ICache/DCache functions ;//========================= ;//void MMU_InvalidateIDCache(void) EXPORT MMU_InvalidateIDCache MMU_InvalidateIDCache mcr p15,0,r0,c7,c7,0 MOV_PC_LR ;//void MMU_InvalidateICache(void) EXPORT MMU_InvalidateICache MMU_InvalidateICache mcr p15,0,r0,c7,c5,0 MOV_PC_LR ;//void MMU_InvalidateICacheMVA(U32 mva) EXPORT MMU_InvalidateICacheMVA MMU_InvalidateICacheMVA ;//r0=mva mcr p15,0,r0,c7,c5,1 MOV_PC_LR ;//void MMU_PrefetchICacheMVA(U32 mva) EXPORT MMU_PrefetchICacheMVA MMU_PrefetchICacheMVA ;//r0=mva mcr p15,0,r0,c7,c13,1 MOV_PC_LR ;//void MMU_InvalidateDCache(void) EXPORT MMU_InvalidateDCache MMU_InvalidateDCache mcr p15,0,r0,c7,c6,0 MOV_PC_LR ;//void MMU_InvalidateDCacheMVA(U32 mva) EXPORT MMU_InvalidateDCacheMVA MMU_InvalidateDCacheMVA ;//r0=mva mcr p15,0,r0,c7,c6,1 MOV_PC_LR ;//void MMU_CleanDCacheMVA(U32 mva) EXPORT MMU_CleanDCacheMVA MMU_CleanDCacheMVA ;r0=mva mcr p15,0,r0,c7,c10,1 MOV_PC_LR ;//void MMU_CleanInvalidateDCacheMVA(U32 mva) EXPORT MMU_CleanInvalidateDCacheMVA MMU_CleanInvalidateDCacheMVA ;r0=mva mcr p15,0,r0,c7,c14,1 MOV_PC_LR ;//void MMU_CleanDCacheIndex(U32 index) EXPORT MMU_CleanDCacheIndex MMU_CleanDCacheIndex ;r0=index mcr p15,0,r0,c7,c10,2 MOV_PC_LR ;//void MMU_CleanInvalidateDCacheIndex(U32 index) EXPORT MMU_CleanInvalidateDCacheIndex MMU_CleanInvalidateDCacheIndex ;r0=index mcr p15,0,r0,c7,c14,2 MOV_PC_LR ;//void MMU_WaitForInterrupt(void) EXPORT MMU_WaitForInterrupt MMU_WaitForInterrupt mcr p15,0,r0,c7,c0,4 MOV_PC_LR ;//=============== ;// TLB functions ;//=============== ;//voic MMU_InvalidateTLB(void) EXPORT MMU_InvalidateTLB MMU_InvalidateTLB mcr p15,0,r0,c8,c7,0 MOV_PC_LR ;//void MMU_InvalidateITLB(void) EXPORT MMU_InvalidateITLB MMU_InvalidateITLB mcr p15,0,r0,c8,c5,0 MOV_PC_LR ;//void MMU_InvalidateITLBMVA(U32 mva) EXPORT MMU_InvalidateITLBMVA MMU_InvalidateITLBMVA ;//ro=mva mcr p15,0,r0,c8,c5,1 MOV_PC_LR ;//void MMU_InvalidateDTLB(void) EXPORT MMU_InvalidateDTLB MMU_InvalidateDTLB mcr p15,0,r0,c8,c6,0 MOV_PC_LR ;//void MMU_InvalidateDTLBMVA(U32 mva) EXPORT MMU_InvalidateDTLBMVA MMU_InvalidateDTLBMVA ;//r0=mva mcr p15,0,r0,c8,c6,1 MOV_PC_LR ;//================= ;// Cache lock down ;//================= ;//void MMU_SetDCacheLockdownBase(U32 base) EXPORT MMU_SetDCacheLockdownBase MMU_SetDCacheLockdownBase ;//r0= victim & lockdown base mcr p15,0,r0,c9,c0,0 MOV_PC_LR ;//void MMU_SetICacheLockdownBase(U32 base) EXPORT MMU_SetICacheLockdownBase MMU_SetICacheLockdownBase ;//r0= victim & lockdown base mcr p15,0,r0,c9,c0,1 MOV_PC_LR ;//================= ;// TLB lock down ;//================= ;//void MMU_SetDTLBLockdown(U32 baseVictim) EXPORT MMU_SetDTLBLockdown MMU_SetDTLBLockdown ;//r0= baseVictim mcr p15,0,r0,c10,c0,0 MOV_PC_LR ;//void MMU_SetITLBLockdown(U32 baseVictim) EXPORT MMU_SetITLBLockdown MMU_SetITLBLockdown ;//r0= baseVictim mcr p15,0,r0,c10,c0,1 MOV_PC_LR ;//============ ;// Process ID ;//============ ;//void MMU_SetProcessId(U32 pid) EXPORT MMU_SetProcessId MMU_SetProcessId ;//r0= pid mcr p15,0,r0,c13,c0,0 MOV_PC_LR END

ARM11 (S3C6410) CP15寄存器

s3c6410中断程序其中包括汇编代码和C代码，以及代码注释

实现一个简单的加减法运算，Linux下ARM汇编与C语言混编

CP15协处理器的使用方法CP15协处理器的使用方法CP15协处理器的使用方法CP15协处理器的使用方法CP15协处理器的使用方法

驱动开发/核心开发

21,618

社区成员

21,710

社区内容

发帖

与我相关

我的任务

社区管理员

加入社区

近7日
近30日
至今

加载中

查看更多榜单

社区公告

暂无公告

试试用AI创作助手写篇文章吧

+ 用AI写文章