我用的是modelsim编译，但有错误，不会啊，各位大哥帮帮小弟啊

[xiaoze2096]

LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY lpm;
USE lpm.lpm_components.all;

ENTITY lpm_mux0 IS
PORT
(
data0x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
sel : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
END lpm_mux0;


ARCHITECTURE SYN OF lpm_mux0 IS

-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_2D (1 DOWNTO 0, 11 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (11 DOWNTO 0);

BEGIN
sub_wire5 <= data0x(11 DOWNTO 0);
result <= sub_wire0(11 DOWNTO 0);
sub_wire1 <= sel;
sub_wire2(0) <= sub_wire1;
sub_wire3 <= data1x(11 DOWNTO 0);
sub_wire4(1, 0) <= sub_wire3(0);
sub_wire4(1, 1) <= sub_wire3(1);
sub_wire4(1, 2) <= sub_wire3(2);
sub_wire4(1, 3) <= sub_wire3(3);
sub_wire4(1, 4) <= sub_wire3(4);
sub_wire4(1, 5) <= sub_wire3(5);
sub_wire4(1, 6) <= sub_wire3(6);
sub_wire4(1, 7) <= sub_wire3(7);
sub_wire4(1, 8) <= sub_wire3(8);
sub_wire4(1, 9) <= sub_wire3(9);
sub_wire4(1, 10) <= sub_wire3(10);
sub_wire4(1, 11) <= sub_wire3(11);
sub_wire4(0, 0) <= sub_wire5(0);
sub_wire4(0, 1) <= sub_wire5(1);
sub_wire4(0, 2) <= sub_wire5(2);
sub_wire4(0, 3) <= sub_wire5(3);
sub_wire4(0, 4) <= sub_wire5(4);
sub_wire4(0, 5) <= sub_wire5(5);
sub_wire4(0, 6) <= sub_wire5(6);
sub_wire4(0, 7) <= sub_wire5(7);
sub_wire4(0, 8) <= sub_wire5(8);
sub_wire4(0, 9) <= sub_wire5(9);
sub_wire4(0, 10) <= sub_wire5(10);
sub_wire4(0, 11) <= sub_wire5(11);

lpm_mux_component : lpm_mux
GENERIC MAP (
lpm_size => 2,
lpm_type => "LPM_MUX",
lpm_width => 12,
lpm_widths => 1
)
PORT MAP (
sel => sub_wire2,
data => sub_wire4,
result => sub_wire0
);
END SYN;

编译时出现下面的错误，不会解决啊
** Error: C:/Modeltech_6.1f/altera/src/liu_fpga12-18FIANAL/lpm_mux0.vhd(61): (vcom-1089) Only one discrete range allowed in slice name of "std_logic_2d".
** Error: C:/Modeltech_6.1f/altera/src/liu_fpga12-18FIANAL/lpm_mux0.vhd(61): (vcom-1136) Unknown identifier "std_logic_2d".
** Error: C:/Modeltech_6.1f/altera/src/liu_fpga12-18FIANAL/lpm_mux0.vhd(95): (vcom-1141) Identifier "lpm_mux" does not identify a component declaration.
** Error: C:/Modeltech_6.1f/altera/src/liu_fpga12-18FIANAL/lpm_mux0.vhd(110): VHDL Compiler exiting

[哈皮歪詩]

First of all, this board is for WinCE. I don't see the reason you post your VHDL question here.

Secondly, where is the component declaration of "lpm_mux" ? It is missing in your code.

[xiaoze2096]

能再说得明白点吗？我不知道怎么改过来

[哈皮歪詩]

My understanding is that you are supposed to have something like:

component lpm_mux
....

end component


in your code. Where is the port list of lpm_mux? How is lpm_mux defined?