DP83848 PHY芯片100Mbps连续通讯会断开，10M很稳定

Youngfon 2011-10-17 10:14:43

LPC2478+dp83848,配置如下，100Mbps连续通讯会断开，10M时很稳定，不知问题出在哪里。用抓包工具可以抓到100M断开时以太网控制帧为[FIN+ACK],然后是[RST]的控制字信息，无法断定是硬件还是软件出的问题。盼高手解决。

void InitNic(uint8 num)
{
uint32 i;

PCONP |= 0X40000000;

/* Set the PIN to RMII */
//////
//i = rMAC_MODULEID;
//if(i == OLD_EMAC_MODULE_ID)
// PINSEL2 |= 0x50151105; /* selects P1[0,1,4,6,8,9,10,14,15] */
//else
// PINSEL2 |= 0x50150105; /* selects P1[0,1,4,8,9,10,14,15] */
//PINSEL3 |= 0x00000005; /* selects P1[17:16] */
//////

/* Set the PIN to MII */
i = rMAC_MODULEID;
if(i == OLD_EMAC_MODULE_ID)
PINSEL2 |= 0x55555555;
else
PINSEL2 |= 0x55554555;
PINSEL3 |= 0x00000005; /* selects P1[17:16] */

/* reset : soft,simulation,mcs/rx,rx,mcs/tx,tx */
MAC_MAC1 = 0xCF00; /* [15],[14],[11:8] -> soft resets all MAC internal modules */

/* RegReset,TxReset,RxReset */
MAC_COMMAND = 0x0038; /* reset all datapaths and host registers */

for ( i = 0; i < 0x40; i++ ); /* short delay after reset ,required 3us*/

MAC_MAC1 = 0x0; /* deassert all of the above soft resets in MAC1 */

EMAC_TxDisable();
EMAC_RxDisable();

MAC_MAC2 = 0x00; /* initialize MAC2 register to default value */

/* Non back to back inter-packet gap */
MAC_IPGR = 0x0012; /* use the default value recommended in the users manual */

MAC_CLRT = 0x370F; /* Use the default value in the users manual */
MAC_MAXF = 0x0600; /* Use the default value in the users manual */

/* PHY Select RMII */
//rECOMMAND |= (1<<9); /* rECOMMAND and rMCFG registers(defined in old version) = MAC_COMMAND and MAC_MCFG*/

/* Initial MII Mgmt */
//rMCFG |= (7<<2) + 1; /* clk div 28,address increment */
//MAC_MCFG = 0x801d;
//MAC_MCFG |= 0x0019; /* host clock divided by 20, no suppress preamble, no scan increment */
//MAC_MCFG |= 0x0018; /* div by 20 */
MAC_MCFG |= 0x001c; /* div by 28 */

/* RMII or MII configuration */
//MAC_COMMAND |= 0x0200;
//MAC_COMMAND = 0x0240; /* bit9=1 select RMII mode*/
MAC_COMMAND = 0x0440; /* bit9=0 select MII mode,bit10=1 select full duplex*/

//MAC_SUPP = 0x0900; /* RMII setting, PHY support: [8]=0 ->10 Mbps mode, =1 -> 100 Mbps mode */
/* (note bit 4 was set in original test, although spec says its unused) */
//for ( i = 0; i < 0x20; i++ ); /* short delay */
//MAC_SUPP = 0x0100;
MAC_SUPP = 0x0000; /* used for RMII mode, bit8=0,10M; =1,100M*/

// probe phy address
for(i=0;i<32;i++)
{
PHYID = Read_PHY(i , 2 );
if(PHYID == 0x2000)
break;
}
if(i >= 32)
while(1) ;

PHYID = i;
// PHY RESET
Write_PHY(PHYID, 0, 0xb300 ); /* reset PHY, enable auto-neg(10M/_100M,half/_full dulex)*/
//Write_PHY(PHYID, 4, 0x0061 ); /* auto-neg, select 10M/full dulex */
do
{
OSTimeDly(OS_TICKS_PER_SEC);
RstWdt(); /* 喂狗*/
tempreg = Read_PHY(PHYID, 0x01 ); /* 01h-bit5 or 10h-bit4 indicate auto-neg complete*/
if(tempreg&0x0020) /* wait auto-neg complete */
break;
}while(1);

OSTimeDly(OS_TICKS_PER_SEC);
RstWdt(); /* 喂狗*/
tempreg = Read_PHY(PHYID, 0x10 ); /* read the result of auto-neg */
//for(i=0;i<32;i++)
// PHYREG[i] = Read_PHY(PHYID ,i );
tempreg &= 0x0006;
/* INPUT MAC ADDRESS */
SetMacID(NetPort[num].My_Mac);

if(tempreg == 0x0004)//100fdx
{
dulxp = 1;
speed = 100;
MAC_MAC2 = 0x31; /* full duplex, CRC and PAD enabled. */
MAC_SUPP |= 0x0100; /* MII Support Reg. speed is set to 100M */
MAC_COMMAND |= 0x0440;
/* back to back int-packet gap */
MAC_IPGT = 0x0015; /* IPG setting in full duplex mode */
}
else if(tempreg == 0x0000)//100hdx
{
dulxp = 0;
speed = 100;
MAC_MAC2 = 0x30; /* half duplex, CRC and PAD enabled. */
MAC_SUPP |= 0x0100; /* MII Support Reg. speed is set to 100M */
MAC_COMMAND |= 0x0040;
/* back to back int-packet gap */
MAC_IPGT = 0x0012; /* IPG setting in half duplex mode */
}
else if(tempreg == 0x0006)//10fdx
{
dulxp = 1;
speed = 10;
MAC_MAC2 = 0x31; /* full duplex, CRC and PAD enabled. */
MAC_SUPP = 0; /* MII Support Reg. speed is set to 10M */
MAC_COMMAND |= 0x0440;
/* back to back int-packet gap */
MAC_IPGT = 0x0015; /* IPG setting in full duplex mode */
}
else if(tempreg == 0x0002)//10hdx
{
dulxp = 0;
speed = 10;
MAC_MAC2 = 0x30; /* half duplex, CRC and PAD enabled. */
MAC_SUPP = 0; /* MII Support Reg. speed is set to 10M */
MAC_COMMAND |= 0x0040;
/* back to back int-packet gap */
MAC_IPGT = 0x0012; /* IPG setting in half duplex mode */
}
EMACTxDescriptorInit();
EMACRxDescriptorInit();

MAC_MAC1 |= 0x0002; /* bit[1]-Pass All Rx Frame */

/* Set up RX filter, accept broadcast and perfect station */
MAC_RXFILTERCTRL = 0x0022; /* bit[1]-accept broadcast, bit[5]-accept perfect */
MAC_RXFILTERCTRL |= 0x0005; /* bit[2]-MULTICAST FRAME, bit[0]-UNICAST FRAME */
MAC_RXFILTERCTRL |= 0x0018; /* bit[4:3]-ENABLE_HASH */

MAC_INTCLEAR = 0xFFFF; /* clear all MAC interrupts */
/* MAC interrupt related register setting */
//////
//if ( install_irq( EMAC_INT, (void *)EMACHandler, HIGHEST_PRIORITY ) == FALSE )
//{
// return (FALSE);
//}
//////
EMAC_RxEnable();
EMAC_TxEnable();
LINKSTATUS = 1;
EINTSTA = 0;
SetVICIRQ(21, 5, (unsigned int)Ethernet_Exception);

MAC_INTENABLE = 0x000c; /* Enable all interrupts except SOFTINT and WOL */

}

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