求教verilog秒表
求教大神:我现在写了一秒表
这是计数块(由于篇幅限制,秒,小时的计数省略):
always@(negedge reset or posedge clk_out )
if(!reset)
begin
co[0]<=0;
Millisecond<=0;
end
else if( Millisecond==7'd99)
begin
co[0]<=1;
Millisecond<=7'd0;
end
else begin
co[0]<=0;
Millisecond<= Millisecond+7'd1;
end
下面这个是存数模块:(即每来一个POS记一个人的时间,只记三个人的时间)
always@(posedge POS or negedge reset)
if(!reset)
begin
M<=2'd0;
Memory[0]<=0;
Memory[1]<=0;
Memory[2]<=0;
end
else if( M==2'd0)
begin
Memory[0]<={Hour, Minute,Second,Millisecond};
M <= M+2'd1;
end
else if( M==2'd1)
begin
Memory[1]<={Hour, Minute,Second,Millisecond};
M <= M+2'd1;
end
else if( M==2'd2)
begin
Memory[2]<={Hour, Minute,Second,Millisecond};
M <= 2'd0;
end
else
M<=2'd0;
下面是显示计数模块(即每摁一次SHOW,显示一次成绩)
always@(posedge SHOW or negedge reset )
if(!reset)
SH<=2'd0;
else if(SH==2'd0)
begin
{Hour, Minute,Second,Millisecond}<= Memory[0];
SH<= SH+2'd1;
end
else if(SH==2'd1)
begin
{Hour, Minute,Second,Millisecond}<= Memory[1];
SH<=SH+2'd1;
end
else if(SH==2'd2)
begin
{Hour, Minute,Second,Millisecond}<= Memory[2];
SH<= 2'd0;
end
else
SH<=2'd0;
endmodule
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问题是用赛灵思ISE综合是不能在两个always块中对同一变量赋值(即Hour, Minute,Second,Millisecond),该怎么改代码呢?