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-> vxbPciHeaderShow 0x0034e750,1,0,0
vendor ID = 0x1095
device ID = 0x3132
command register = 0x0007
status register = 0x0010
revision ID = 0x01
class code = 0x01
sub class code = 0x80
programming interface = 0x00
cache line = 0x08
latency time = 0x00
header type = 0x00
BIST = 0x00
base address 0 = 0xa4000004
base address 1 = 0x00000000
base address 2 = 0xa4004004
base address 3 = 0x00000000
base address 4 = 0xa8000001
base address 5 = 0x00000000
cardBus CIS pointer = 0x00000000
sub system vendor ID = 0x1095
sub system ID = 0x3132
expansion ROM base address = 0x00000000
interrupt line = 0x08
interrupt pin = 0x01
min Grant = 0x00
max Latency = 0x00
Capabilities - Power Management
Capabilities - Message Signaled Interrupts: 0x5c control 0x80 Disabled, 64-bit, MME: 0 MMC: 0
Address: 0000000000000000 Data: 0x0000
Per-vector Mask: Unsupported
Capabilities - PCIe: Legacy Endpoint, IRQ 0
Device: Max Payload: 1024 bytes, Extended Tag: 5-bit
Acceptable Latency: L0 - <64ns, L1 - <1us
Errors Enabled:
Max Read Request 512 bytes
Link: MAX Speed - 2.5Gb/s, MAX Width - by 1 Port - 0 ASPM - L0s
Latency: L0s - >4us, L1 - >64us
ASPM - Disabled, RCB - 64bytes
Speed - 2.5Gb/s, Width - by 1
Ext Capabilities - Advanced Error Reporting. 0x100. Version 1. AER Control: 0xa0
Uncorrectable : Mask 0x0. Severity 0x62011
Uncorrectable Status:
Correctable : Mask 0x0.
Correctable Status:
HeaderLog:
Error Source Identification: 0x0 0x0
value = 0 = 0x0