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library ieee;
use ieee.std_logic_1164.all;
entity r_s is
port(r,s,cp: in std_logic;
q,qb: out std_logic);
end r_s;
architecture behav of r_s is
signal rs : std_logic_vector(1 downto 0);
signal q_s,qb_s: std_logic;
begin
rs<=s&r;
process(rs,cp)
begin
if cp'event and cp='1' then
if rs="11" then q_s<=q_s;qb_s<=qb_s;
elsif rs="01" then q_s<=not q_s;qb_s<='1';
elsif rs="10" then q_s<=not q_s;qb_s<='0';
elsif rs="00" then q_s<=not q_s;qb_s<='X';
end if;
end if;
end process;
q<=q_s;qb<=qb_s;
end behav;