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Who can explain me stack based machine & instruction-level-parallelism.
Cheers,
Cheers,
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cc9hwa 2001-12-29
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Hi nomy(),
How are you doing? May I have your e-mail, so that we can talk about more details. In addition, could you please introduce me some website/book/journal concentrating upon the topics (stack based machine and nstruction-level-parallelism).
I really need you help. By the way, where are you?
Your sincerely,
cc9hwa
cc9hwa@hotmail.com
How are you doing? May I have your e-mail, so that we can talk about more details. In addition, could you please introduce me some website/book/journal concentrating upon the topics (stack based machine and nstruction-level-parallelism).
I really need you help. By the way, where are you?
Your sincerely,
cc9hwa
cc9hwa@hotmail.com
Roage 2001-12-25
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!!!!!!你不能打中文，但可以看到？中文？？？
不是吧，用复制，粘贴，就可以了嘛。呵呵..........
不是吧，用复制，粘贴，就可以了嘛。呵呵..........
chinananchang 2001-12-25
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u guy,happy to see ur words.u can't laugh at these replies to ur note because we are chinese after all.right?r u majored in computer science in U.K?
nomy 2001-12-25
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stack based chip: 80x87
instruction-level-parallelism: alpha 21064(super scaler), (MIPS,Delux)pipeline
the stack based chip provides machine laguage such as push, pop, add, ...
you can add two doubles with such codes:
push v1 //v1 to stack
push v2 //v2 to stack
add //v1 and v2 poped out, v1+v2 on stack top
instruction-level-parallelism means that we want to increase the performance of
the machine by execute more than one instruction at the same time.
the pipelining mechanism split an instruction execution into multiple stages,
the cpu can execute multiple instructions in different stages.
for example, if we have five stages(1--5), we can have five instructions run at
the same time: one on stage1, one on 2, one on 3...
delux has five stages:instruction fetch, decode, execute, read mm, write back.
the super scaler machines are based on pipelining, but has multiple processing
units in execute stage.
I think you should read books on computer architechture and pay more attention
on instruction set design.
instruction-level-parallelism: alpha 21064(super scaler), (MIPS,Delux)pipeline
the stack based chip provides machine laguage such as push, pop, add, ...
you can add two doubles with such codes:
push v1 //v1 to stack
push v2 //v2 to stack
add //v1 and v2 poped out, v1+v2 on stack top
instruction-level-parallelism means that we want to increase the performance of
the machine by execute more than one instruction at the same time.
the pipelining mechanism split an instruction execution into multiple stages,
the cpu can execute multiple instructions in different stages.
for example, if we have five stages(1--5), we can have five instructions run at
the same time: one on stage1, one on 2, one on 3...
delux has five stages:instruction fetch, decode, execute, read mm, write back.
the super scaler machines are based on pipelining, but has multiple processing
units in execute stage.
I think you should read books on computer architechture and pay more attention
on instruction set design.
cc9hwa 2001-12-24
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I am in U.K. I can't type Chinese at the moment.
"Cherrs" means Thank you.
"Cherrs" means Thank you.
leizhengdeng 2001-12-21
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cheers 人名？
leizhengdeng 2001-12-21
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谁能解释基于栈的机器和指令级并行，不知道翻译得对不对
hellen104 2001-12-21
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"Who can explain me stack based machine & instruction-level-parallelism.
Cheers"
这是什么意思？？？,
Cheers"
这是什么意思？？？,
cc9hwa 2001-12-21
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I am so sorry about that, I cannot ask questions in Chinese.
Linux2001 2001-12-21
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不要用英语提问
rhesus 2001-12-21
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Cheers是举杯敬酒的用语
bluetooth_2001 2001-12-21
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to cc9hwa(rubbish):Where are you from?(in csdn don't speak chinese,i faint)
szlbyou 2001-12-21
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ft
sqlalchemy使用内连接报错Please use the .select_from() method to establish an explicit left side, as well as
