stack based chip: 80x87
instruction-level-parallelism: alpha 21064(super scaler), (MIPS,Delux)pipeline
the stack based chip provides machine laguage such as push, pop, add, ...
you can add two doubles with such codes:
push v1 //v1 to stack
push v2 //v2 to stack
add //v1 and v2 poped out, v1+v2 on stack top
instruction-level-parallelism means that we want to increase the performance of
the machine by execute more than one instruction at the same time.
the pipelining mechanism split an instruction execution into multiple stages,
the cpu can execute multiple instructions in different stages.
for example, if we have five stages(1--5), we can have five instructions run at
the same time: one on stage1, one on 2, one on 3...
delux has five stages:instruction fetch, decode, execute, read mm, write back.
the super scaler machines are based on pipelining, but has multiple processing
units in execute stage.
I think you should read books on computer architechture and pay more attention
on instruction set design.