如何解决LCD内部pixel clock frequency？

下雨天不要穿洞洞鞋 2022-08-17 09:38:10

如何解决LCD内部pixel clock frequency？

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配置不对导致的LCD一半显示正常，一半不正常花屏条纹闪烁
以novatek为例调整这以下三个寄存器的刷新时间可以解决问题。
DisplayTiming Control in Normal / Idle Off Mode (BD00hBD04h)
DisplayTiming Control in Idle On Mode (BE00hBE04h)
DisplayTiming Control in Partial / Idle Off Mode (BF00h~BF04h)

CH7034B Fulll Datasheet Rev1.25 CH7034B HDTV/VGA/LVDS Encoder Supports multiple output display formats – including Component YPrPb(HDTV), LVDS and analog RGB (VGA) • Three 10-bit high speed DACs • HDTV output support up to 1080p • Analog RGB (VGA) support up to 1920x1080 resolution • Single channel LVDS 18-bit transmitter supports input resolution up to 1366x768 • Support scaled and bypassed video streams output from VGA/HDTV and LVDS interfaces simultaneously • Supports panel protection, power sequencing and backlight on/off. PWM is available for controlling LCD brightness • TV/Monitor connection detect capability. DACs can be switched off through programming internal registers • On-chip SDRAM frame buffer to support frame rate conversion. • Programmable adaptive de-flickering filter • Supports 8/12/16/18/24-bit parallel interface inputs for either RGB format or YCbCr format (ITU-R 656 or ITU-R 601). 80/86 MPU interface and DE only mode are also supported. • Wide range of input resolutions support for up to 1366x768 (i.e. 640x480 720x480, 720x576, 800x600, 1024x600, 1024x768, 1280x800, and etc.) • Image display rotation support at 90/180/270 degree or flipped in horizontal/vertical position • Pixel-level color enhancement for brightness, contrast, hue and saturation adjustment for HDTV • Horizontal/vertical position adjusted through serial port programming • Pixel clock input frequency support for up to 165 MHz • Flexible crystal or oscillator clock input frequency (2.3MHz – 64MHz) • IO Supply Voltages from 1.2V to 3.3V and SPC/SPD Supply Voltages from 1.8V to 3.3V. • Programmable power management • Device fully programmable through serial port or can automatically load firmware from Chrontel Boot ROM (9904AMF) • Offered in a 88-pin QFN package Chrontel CH7034B is specifically designed for a portable system that requires connections to LCD display, High Definition Television (HDTV) or RGB (VGA) monitor. With its advanced video encoder, flexible scaling engine and easy-to-configure video interface, the CH7034B satisfies manufactures’ product display requirements and reduces their costs of development and time-to-market.

DE2 web serve的源代码 Overview: - This design is based on the Nios II/f core and provides a typical mix of peripherals and memories as well as a video pipeline. The SOPC Builder system provides an interface to each hardware component on the embedded evaluation kit board, such as DDR SDRAM, LEDs, RS-232 connector, and the Ethernet MAC/10/100 PHY as well as the 800 x 240 pixel RGB LCD. There is also a video pipeline which provides high bandwidth memory access that allows for flicker free display on the color LCD. - This is a list of the components available in the system along with a brief description: cpu Nios2/f flash_ssram_pipeline_bridge pipeline_bridge_before_tristate_bridge flash_ssram_tristate_bridge ssram 1 MByte synchronous SRAM ext_flash 16MByte parallel flash ddr_sdram 1 Mbyte DDR SDRAM cpu_ddr_clock_bridge Components on the slow peripheral bridge ========================================= - Components listed here are partitioned off by the use of the slow_peripheral_bridge. This allows non-fmax critical components to be clocked at a slower clock rate to give better fitting for components that are fmax-critical. - The Bridge * slow_peripheral_bridge - The triple speed Ethernet components: * tse_mac * sgdma_tx * sgdma_rx * descriptor_memory - These bridges are here for two reasons: 1) Clock cross between two components that are clocked at a different frequency. * tse_ddr_clock_bridge * tse_ssram_clock_bridge 2) To offset addresses so that the entire memory model is flat. (Every master sees every slave at the same address). * descriptor_offset_bridge - The rest of the components on the slow_peripheral_bridge * sys_clk_timer * performance_counter * jtag_uart * sysid * pll * button_pio * led_pio * pio_id_eeprom_dat * pio_id_eeprom_scl used to access EEProm * remote_update - The following components are used to communicate with the touch panel * touch_panel_spi * touch_panel_pen_irq_n - The sd card solution is provided under license agreement with El Camino (http://www.elcamino.de) * el_camino_sd_card_controller The video pipeline: =================== - The following i2c pins are used to configure the lcd panel for brightness and gamma curves * lcd_i2c_scl * lcd_i2c_en * lcd_i2c_sdat - The rest of the components that make up the video pipeline: * lcd_sgdma * lcd_ta_sgdma_to_fifo * lcd_pixel_fifo * lcd_ta_fifo_to_dfa * lcd_64_to_32_bits_dfa * lcd_pixel_converter * lcd_32_to_8_bits_dfa * lcd_sync_generator Further Notes: ============== - This design contains a PLL that produces a phase-shifted clock to feed the SSRAM. The phase shift is board-dependent, and may be different if this design is retargeted to a different board. - This Quartus II project contains assignments that match the port names produced by SOPC Builder. If you add or modify SOPC Builder components, the pin assignments may no longer be valid. To view the Assignment Editor in the Quartus II software, in the Assignments menu, click "Assignment Editor". - Hardcoded library paths will be inserted into the Quartus settings for this project during system generation due to the presence of the DDR and TSE components. If you intend to modify the hardware and regenerate a system with these components, please remove any old paths from within the project settings file (qsf) IF the project directory has been changed. An example of the absolute paths are shown below: set_global_assignment -name USER_LIBRARIES "C:/niosII_cycloneII_2c35/full_featured;" set_global_assignment -name VHDL_FILE "C:/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_tb_functions.vhd" set_global_assignment -name VHDL_FILE "C:/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_functions.vhd" set_global_assignment -name VHDL_FILE "C:/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_input_buf.vhd" set_global_assignment -name VHDL_FILE "C:/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_timers.vhd" set_global_assignment -name VHDL_FILE "C:/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_avalon_if.vhd" set_global_assignment -name VHDL_FILE "C:/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_bank_details.vhd" set_global_assignment -name VHDL_FILE "C:/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_controller.vhd" set_global_assignment -name VHDL_FILE "C:/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_init.vhd" set_global_assignment -name VERILOG_FILE "C:/niosII_cycloneII_2c35/full_featured/ddr_sdram_auk_ddr_dqs_group.v" set_global_assignment -name VERILOG_FILE "C:/niosII_cycloneII_2c35/full_featured/ddr_sdram_auk_ddr_clk_gen.v" set_global_assignment -name VERILOG_FILE "C:/niosII_cycloneII_2c35/full_featured/ddr_sdram_auk_ddr_datapath.v" set_global_assignment -name VERILOG_FILE "C:/niosII_cycloneII_2c35/full_featured/ddr_sdram_auk_ddr_sdram.v" set_global_assignment -name VERILOG_FILE "C:/niosII_cycloneII_2c35/full_featured/ddr_sdram.v" * These paths have been pre-removed in the qsf of the designs shipped in the installation. - DDR memory is the main memory of the system, however SSRAM has a faster access speed (when using the same clock frequencies). - The current version of the Nios II EDS hardware design example uses an HDL file as the top level of the design hierarchy. If you would like to use a schematic-based top level instead (BDF), follow the steps listed below. 1) In the Quartus II software, open the top-level HDL file (.v or .vhd) for the design. 2) Create a symbol for the HDL file by clicking File -> Create/Update -> Create Symbol Files for Current File 3) Create a new BDF file by clicking File -> New -> Block Diagram/Schematic File. 4) Instantiate the symbol in the BDF by double-clicking in the empty space of the BDF file and selecting "Project -> " 5) Instantiate pins in the BDF by double-clicking empty space, then typing "input", "output", or "bidir". 6) Rename the pins and connect them to the appropriate ports on the symbol. 7) Save the BDF as a unique filename. 8) Set the BDF as your top level entity by clicking: Project -> Set as Top-Level Entity 9) Recompile the Quartus II project. For more information and details, refer to the Nios II Embedded Design Suite Release Note.

ILI9225B_DS_V03.pdf

帧同步信号，每发出一个脉冲就意味着新的一屏图像数据开始发送，行同步信号，每发出一个脉冲意味着新的一行图像数据开始发送。在帧同步和行同步中，必须留有回扫时间。这个时序安排也是由于 CRT 显示器电子枪偏转所需要的时间，现在不需要，只不过是所谓的行业标准如下图所示，上边界和下边界就是帧的回扫时间左边界和右边界就是行的回扫时

先说明下像素时钟pixclock的概念（以下转自：http://bbs.csdn.net/topics/390340382?page=1） pixclock=1/dotclock 其中dotclock是视频硬件在显示器上绘制像素的速率 dotclock=(x向分辨率+左空边+右空边+HSYNC长度)* (y向分辨率+上空边+下空边+YSYNC长度)*整屏的刷新率其中x向分辨率、左空边、右空边...

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